Original title: FPGA-based fault simulator
Translated title: Simulátor chyb založený na programovatelném logickém obvodu
Authors: Kafka, Leoš ; Novák, O.
Document type: Papers
Conference/Event: DDECS 2006. IEEE Design and Diagnostics of Electronic Circuits and Systems, Prague (CZ), 2006-04-18 / 2006-04-21
Year: 2006
Language: eng
Abstract: [eng] [cze]
This paper describes a simulator based an this technique and show that partial dynamic reconfiguration is an effective way of falut injection. Error-detection-code based CED circuits are used in experiments; the results of the experiments are reported. Článek presentuje simulátor chyb založený na programovatelném logickém poli.
Keywords: falut simulation; FPGA; reconfiguartion
Project no.: CEZ:AV0Z10750506 (CEP), 1QS108040510 (CEP)
Funding provider: GA AV ČR
Host item entry: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems, ISBN 1-4244-0184-4

Institution: Institute of Information Theory and Automation AS ČR (web)
Document availability information: Fulltext is available at the institute of the Academy of Sciences.
Original record: http://hdl.handle.net/11104/0134006

Permalink: http://www.nusl.cz/ntk/nusl-35467


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Research > Institutes ASCR > Institute of Information Theory and Automation
Conference materials > Papers