National Repository of Grey Literature 3 records found  Search took 0.00 seconds. 
A portal to support the teaching of applied cryptography
Vojáčková, Veronika ; Sikora, Marek (referee) ; Zeman, Václav (advisor)
Cryptography has a rich history, ranging from ancient civilizations to modern times, ensuring confidentiality and security has always played a very important role. In order to understand these algorithms, however, it is necessary to understand the basics of this issue, which can be a very difficult task without comprehensive resources. The thesis first examines web portals dealing with cryptography on the Czech and foreign Internet. Next, it compiles all the necessary knowledge for the subject of applied cryptography. As part of the work, a web portal is created bringing together the necessary information to support teaching along with a practical demonstration of algorithms and their use in the Python programming language.
Web application for file encryption
Tatar, Martin ; Blažek, Petr (referee) ; Zeman, Václav (advisor)
The bachelor thesis is focused on developing a web application for file encryption. In the theoretical part symmetric encryption algorithms are divided into block ciphers and stream ciphers. Selected ciphers are described and their properties are compared. Then the modes of operation for block ciphers are described. The developed application encrypts both files and text inputs by the selected algorithm and can operate in various modes of operation. In addition to this functionality the application is supplemented with descriptions of available ciphers and modes of operation.
Simulation of cryptographic algorithms using FPGA
Németh, František ; Mašek, Jan (referee) ; Smékal, David (advisor)
Bachelor thesis is dealing with a cipher standard AES and with a design of encryption and decryption components for AES in special modes of operation. Programming language is VHDL. In theoretical part of thesis is a further descriptions of AES and behaviour of block cipher operation modes. Furthermore the brief description of VHDL, FPGA and NetCOPE framework is a piece of theoretical part as well. The practical part contains designs which are made in developing environment Vivado from Xilinx. Programmed modes of operation are ECB, CBC, CTR and CFB. Simulation outputs and synthesis results are summerized in tables.