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Effective Optical Function in Fibre Photonics Networks
Havliš, Ondřej ; Vlček, Čestmír (referee) ; Dostál, Otto (referee) ; Slavíček, Karel (advisor)
This dissertation focuses on efficient optical functions in fiber photonic networks, testbeds and multiband polygon. These functions include optical amplification, switching, routing and filtering of the optical spectrum. The theoretical part of the thesis deals with optical amplification, where different types of optical amplifiers are described. These employ various principles for their function, such as the use of Raman scattering, rare earth doped fibers – primarily Erbium, and lastly semiconductor structures. The practical part of the work is focused on the use and verification of efficient optical functions and their services, i.e. transmission of classical telecommunication data and transmission of ultra-stable quantities (transmission of accurate time and ultra-stable frequency) in fiber photonic network, testbeds and multiband polygon.
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Implementation of a Boot Controller for Intel FPGAs
Hak, Tomáš ; Fukač, Tomáš (referee) ; Matoušek, Jiří (advisor)
This thesis touches the topic of using FPGA technology in the field of computer networks, specifically for hardware acceleration of network traffic processing on a network card developed by the CESNET association. FPGA technology is popular mainly due to the possibility to easily reconfigure the chip and fix any errors or update the firmware. The thesis first discusses the design and implementation of a new unit for Intel FPGA, which will be able to communicate with the external configuration flash memory of the chip featured on the card mentioned above. It then goes on to address the design and implementation of a software tool that will allow, via the newly implemented firmware unit, to load new configuration data into the flash memory and force reconfiguration of the FPGA chip using this newly loaded data. Towards the end of the thesis, the functionality of the newly implemented system is tested in practice.
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Netdev Driver for Acceleration COMBO Cards
Tran, Dominik ; Vrána, Roman (referee) ; Kučera, Jan (advisor)
This thesis deals with the development of the network device driver for the FPGA network COMBO cards, which should enable receiving and sending packets through standard network interface of Linux kernel. CESNET is developing a device called DDoS Protector for protection against an amplification (D)DoS attacks, which uses COMBO cards to achieve high performance. A SZE2 interface is used for high speed transfers of network data between COMBO card and a controlling software application, using technique of bypassing kernel network stack and other methods. DDoS Protector has to support standard network protocols, whose implementation directly on top of the SZE2 is very difficult. Instead, using kernel network stack, which is, by default, bypassed to achieve high performance, is much easier to implement and supports all sorts of protocols. Creation of the network device driver enables us to use kernel network stack and other network applications for COMBO cards. Based on the study of SZE2 interface and driver development, I designed and then successfully implemented network device driver. Driver was tested to ensure standard protocols work. It was also tested from the performance point of view. I have also developed the same type of driver for the newer interface - NDP and an application for an accelerated packet forwarding, both of which are functional and were not part of the thesis specification.
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Applied use of DSP blocks in Intel FPGA
Kondys, Daniel ; Pokorný, Jiří (referee) ; Smékal, David (advisor)
This bachelor's thesis explores the utilization of DSP blocks located particularly on FPGA Stratix 10 DX 2800 for the implementation of a counter and a comparator. In the theoretical part, topics such as the protocol Ethernet, the FPGA technology and its relation with Network Interface Controllers are explained, followed by a~description of general design flow for digital circuits on FPGAs and a detailed insight on DSP blocks in the Virtex UltraScale+ XCVU7P and Stratix 10 DX 2800 FPGAs. The practical part focuses on the design, implementation and testing of the counter and comparator, followed by measurements of their impact on FPGA's resource utilization and maximum frequency. Lastly, it describes the integration of these components into modules that are part of the COMBO-400g1 Network Interface Connector firmware and analyzes their impact on FPGA's resource utilization and maximum frequency.
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Hardware-Accelerated Device for Protection Against DoS Attacks
Kuka, Mário ; Kekely, Lukáš (referee) ; Kučera, Jan (advisor)
This thesis deals with the development of a firmware for hardware-accelerated device used as a protection against amplification (D)DoS attacks. In the today's world, (D)DoS attacks are very common and cause significant financial damages. Therefore the goal is to create affordable and easy to deploy centralized device that would resolve this issue. To reach this goal, a hardware accelerator is being used for the high-volume data transfer processing through a single commonly used server. Design and implementation of the firmware had been done considering the fact that this device will be used in the networks with 100\,Gbps speed. The whole system had undergone functional verification and its real throughput was verified within the laboratory testing as well. Created device has been already deployed into the CESNET network infrastructure during the time of the writing of this thesis and it has been tested by the network administrators. Based on the received feedback, the development will continue focusing on expanding of the detection of more types of attacks.
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Implementation of Digital Circuit for High-Speed Network Communication in FPGA
Kondys, Daniel ; Cíbik, Peter (referee) ; Smékal, David (advisor)
Vysokorychlostní síťové karty často obsahují prvky pro hardwarovou akceleraci, která jim umožní efektivně zpracovávat data i při velmi vysokých rychlostech. Tato práce se zabývá tvorbou digitálního obvodu pro FPGA, který bude přenášet Ethernetové rámce rychlostí až 400 Gb/s. K tomu využívá bloky duševního vlastnictví pro Ethernet, které jsou součástí moderních FPGA čipů od firmy Intel. Jedná se o FPGA Stratix 10, které obsahuje bloky duševního vlastnictví typu E-tile, a Agilex, které obsahuje bloky duševního vlastnictví typu F-tile. Před vlastním návrhem se práce zabývá teoretickým rozborem standardu Ethernet a činnostmi jednotlivých podvrstev, popisuje vybrané FPGA čipy a zabývá se i NDK platformou, do níž bude vytvořený obvod zapojen. Praktická část spočívá v konfiguraci daných duševních bloků pro Ethernet a jejich integrací do vytvářeného obvodu. Nakonec jsou popsány metody pro ověření funkčnosti vytvořeného obvodu. Ty zahrnují verifikaci a testy na platformách s danými FPGA čipy. Výsledky ukazují, že vytvořený obvod je funkční a dosahuje rychlosti i 400 Gb/s. Jeho využití spočívá zejména v poskytnutí komunikace přes Ethernet pro digitální obvod, který bude dodáván jako součást firmwaru pro síťovou kartu XpressSX AGI-FH400G vyvinutou sdružením CESNET z.s.p.o a společností REFLEX CES.
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P4 Language-Based Description of Accelerated Device against DoS Attacks
Kuka, Mário ; Kekely, Lukáš (referee) ; Kučera, Jan (advisor)
This thesis describes the development of a networking device used to defend against (D)DoS attacks using P4 language. The main purpose was to design flexible device using P4 lan-guage based on already existing device, this would allow us to quickly react and respond to new more complex DDoS attacks. The design of the device dealt with the transfer of individual parts of the firmware into the P4 language. Subsequently, the entire device firmware was designed for hardware accelerators with FPGA technology. The firmware had been designed with respect to the limitations of current P4 language compilers. The device has been tested under laboratory conditions for functionality and performance. The device will be deployed in the network infrastructure of CESNET.
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Diagnostics and monitoring of transport networks
Maurerová, Lenka ; Horváth, Tomáš (referee) ; Krkoš, Radko (advisor)
Diploma thesis deals with monitoring and diagnostics of transport networks. It focuses on basic diagnostic and surveillance tools, and tools which are developed in the project of Internet2. It is focused on the evaluation of the measurements performed by these tools with a focus on external factors and substandard conditions and their impact on the measurement results.
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Testing of Device for DoS Attack Protection
Burzala, Matúš ; Vrána, Roman (referee) ; Kučera, Jan (advisor)
This thesis deals with testing of a device for (D)DoS protection DCPRO, that is developed within the CESNET association. The aim of the thesis was to design and implement an extendable testing system, which would allow automated testing of DCPRO device. In addition to the testing system, there was created a collection of tests for verification of functional and performance parameters of the device within the thesis. Afterwards, the developed system was integrated into a continuous integration system Jenkins. Particularly within the thesis there were created 109 specific test scenarios to test device firmware modules, 7 throughput test scenarios, 10 test scenarios to verify proper functionality of software modules dedicated to SYN Flood and amplification attacks protection, and one test for verification of device network routing ability. The developed testing system is easily extensible. In order to simplify a future extension of the system, there is a created template encapsulated in source files for new test creation and text part of the thesis contains guide how to create new tests.
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Environment for Testing of DoS Attack Protection Devices
Tran, Dominik ; Vrána, Roman (referee) ; Kučera, Jan (advisor)
This thesis deals with the development of an environment and necessary set of tests for an evaluation of the DDoS Protector device in terms of functionality and performance. CESNET is developing device called DDoS Protector for protection against denial of service (DDoS) attacks with focus on volumetric and TCP SYN flood attacks. Current development environment does not support generation of stateful (TCP) network traffic and it's difficult to create complex evaluation tests in terms of interaction between various parts of the device. Goal of this work is to create an environment which enables complex evaluation of the device, including generation of both stateful and stateless network traffic combined with multi-vector DDoS attack, thus approaching real network traffic. Cisco TRex was chosen after examination of available traffic generators. Finally set of tests generating various combination of legitimate traffic and attacks was created and DDoS Protector was successfully evaluated.
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