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Audio equalizer implementation based on FPGA structure
Otisk, Libor ; Valach, Soběslav (referee) ; Kváš, Marek (advisor)
The bachelor thesis introduces the basic types of audio equalizers. It describes the design of digital filters for graphic equalizer, the correct choice of structure, placement and shape of digital filters. It also describes the implementation of graphic equalizer in the fixed-point arithmetic. It further describes an implementation of the algorithm graphic equalizer on PC and the implementation in gate array of FPGA.
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IMPLEMENTING ALGORITHMS ON FPGA UTILIZING C2H TECHNIQUE
Otisk, Libor ; Bastl, Petr (referee) ; Valach, Soběslav (advisor)
This thesis deals with utilizing C2H technique for implementation algorithm on FPGA. Several structures of digital filters FIR and IIR are implemented within this work with usage of C2H. For such a comparison is in terms of FPGA resources utilized, the maximum frequency, latency, complexity of implementation and acceleration obtained to Nios II processor itself. Example for image processing using local operators implemented using C2h is also created to display the result on the LCD.
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Audio equalizer implementation based on FPGA structure
Otisk, Libor ; Valach, Soběslav (referee) ; Kváš, Marek (advisor)
The bachelor thesis introduces the basic types of audio equalizers. It describes the design of digital filters for graphic equalizer, the correct choice of structure, placement and shape of digital filters. It also describes the implementation of graphic equalizer in the fixed-point arithmetic. It further describes an implementation of the algorithm graphic equalizer on PC and the implementation in gate array of FPGA.
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IMPLEMENTING ALGORITHMS ON FPGA UTILIZING C2H TECHNIQUE
Otisk, Libor ; Bastl, Petr (referee) ; Valach, Soběslav (advisor)
This thesis deals with utilizing C2H technique for implementation algorithm on FPGA. Several structures of digital filters FIR and IIR are implemented within this work with usage of C2H. For such a comparison is in terms of FPGA resources utilized, the maximum frequency, latency, complexity of implementation and acceleration obtained to Nios II processor itself. Example for image processing using local operators implemented using C2h is also created to display the result on the LCD.
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