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SpaceWire Endpoint verification
Peroutka, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of the bachelor´s thesis is the verification of the SpaceWire endpoint IP core created at Department of Microelectronics, Faculty of Electrical Engineering and Communication, VUT Brno. The thesis has 3 major parts. The first part briefly describes the SpaceWire standard. The second part deals with the theoretical description of the verification. The last part deals with the verification of the SpaceWire endpoint.
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Design of digital decimation filter in CMOS technology
Toman, Petr ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
This Master’s thesis deals with digital decimation filter design for undersampling and filtering of sigma-delta ADC signal. Filter cascade is designed in Matlab according to given requirements and is then described in VHDL language aiming for minimum area. Implemented filter functionality is compared to Matlab-generated reference filters in created verification environment. Finally the design is synthesized in specified technology and verified on gate level.
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An Encoder and Decoder of an Error-correction Code for Programmable Read-only Memories
Bareš, Jan ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This work deals with theory of coding, analyses current groups of error correction codes and describes features and parametres of chosen representatives of these groups. By comparing these parametres along with given criteria it choses extended Hamming code as suitable code for securing read-only-memories (ROM). For this code it choses way of realization of synthetisable modules of coder and decoder and describes their design. The work describes design of synthetizable modules of coder and decoder in VHDL. Then it explains functionality of created application which is able to generate these synthetisable modules. For verification of generated modules it creates authentication environment. Part of this environment is also model of ROM allowing writing of any error value into the memory. In the end it automatically verifies generated modules of coder and decoder with various width of input information vector.
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SpaceWire Endpoint verification
Peroutka, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of the bachelor´s thesis is the verification of the SpaceWire endpoint IP core created at Department of Microelectronics, Faculty of Electrical Engineering and Communication, VUT Brno. The thesis has 3 major parts. The first part briefly describes the SpaceWire standard. The second part deals with the theoretical description of the verification. The last part deals with the verification of the SpaceWire endpoint.
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|
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An Encoder and Decoder of an Error-correction Code for Programmable Read-only Memories
Bareš, Jan ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This work deals with theory of coding, analyses current groups of error correction codes and describes features and parametres of chosen representatives of these groups. By comparing these parametres along with given criteria it choses extended Hamming code as suitable code for securing read-only-memories (ROM). For this code it choses way of realization of synthetisable modules of coder and decoder and describes their design. The work describes design of synthetizable modules of coder and decoder in VHDL. Then it explains functionality of created application which is able to generate these synthetisable modules. For verification of generated modules it creates authentication environment. Part of this environment is also model of ROM allowing writing of any error value into the memory. In the end it automatically verifies generated modules of coder and decoder with various width of input information vector.
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Design of digital decimation filter in CMOS technology
Toman, Petr ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
This Master’s thesis deals with digital decimation filter design for undersampling and filtering of sigma-delta ADC signal. Filter cascade is designed in Matlab according to given requirements and is then described in VHDL language aiming for minimum area. Implemented filter functionality is compared to Matlab-generated reference filters in created verification environment. Finally the design is synthesized in specified technology and verified on gate level.
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