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AUTOMATED TESTING OF 10GbE DEVICES
Avramović, Nikola ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Tato práce se zabývá návrhem modelu pro funkční verifikaci a návrhem syntetizovatelného testru 10Gb Ethernet zařízení, které používají XGMII rozhraní. Pro popis modelu je použit programovací jazyk VHDL. Práce zahrnuje vytváření bus functional modelu a návrh testru, který se implementuje jako genericky self-test modul. Výsledný návrh umožňuje verifikaci a testování PHY a MAC vrstve. Pro implementaci testru byla použita vývojová deska DE5-Net osazena FPGA obvodem Stratix V GX od firmy Altera.
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Polymorphic Self-Checking Circuits
Mazuch, Martin ; Růžička, Richard (referee) ; Sekanina, Lukáš (advisor)
This Master's thesis deals with question of the development of self-checking polymorphic circuits. It deals with a traditional way of creating reliable and self-checking circuits, presenting basic principles and methods. Also a method of Cartesian Genetic Programming for development of combinational circuits is explained. This thesis describes concepts of polymorphic gates and circuits and their benefits in practical use. Some existing self-checking polymorphic circuits are presented and their self-checking capabilities are analyzed. A proposal of realization of a design system for self-checking polymorphic circuits is given. A design system has been built based on presented specification and an application allowing simulations and analysis of system-proposed solutions has been created. Variety of experiments have been performed at created system and several interesting solutions have been acquired. At the end, conclusion is given and benefits of MSc. project are discussed.
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AUTOMATED TESTING OF 10GbE DEVICES
Avramović, Nikola ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Tato práce se zabývá návrhem modelu pro funkční verifikaci a návrhem syntetizovatelného testru 10Gb Ethernet zařízení, které používají XGMII rozhraní. Pro popis modelu je použit programovací jazyk VHDL. Práce zahrnuje vytváření bus functional modelu a návrh testru, který se implementuje jako genericky self-test modul. Výsledný návrh umožňuje verifikaci a testování PHY a MAC vrstve. Pro implementaci testru byla použita vývojová deska DE5-Net osazena FPGA obvodem Stratix V GX od firmy Altera.
|
|
|
Polymorphic Self-Checking Circuits
Mazuch, Martin ; Růžička, Richard (referee) ; Sekanina, Lukáš (advisor)
This Master's thesis deals with question of the development of self-checking polymorphic circuits. It deals with a traditional way of creating reliable and self-checking circuits, presenting basic principles and methods. Also a method of Cartesian Genetic Programming for development of combinational circuits is explained. This thesis describes concepts of polymorphic gates and circuits and their benefits in practical use. Some existing self-checking polymorphic circuits are presented and their self-checking capabilities are analyzed. A proposal of realization of a design system for self-checking polymorphic circuits is given. A design system has been built based on presented specification and an application allowing simulations and analysis of system-proposed solutions has been created. Variety of experiments have been performed at created system and several interesting solutions have been acquired. At the end, conclusion is given and benefits of MSc. project are discussed.
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