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Verification of FPGA Generic Interconnection System
Bartoš, Václav ; Martínek, Tomáš (referee) ; Puš, Viktor (advisor)
This thesis deals with design, implementation and realization of simulation verification of generic interconnection system for FPGA chips. This system is part of the NetCOPE platform developed in the Liberouter project, within which was this work done. In the beginning, an usual methods of verification in SystemVerilog language are described. Then there is a brief description of the interconnection system, aimed especially to aspects important to verification. The main part of the thesis is design of verification environment and control program of test for all three components of the tested system. It started form the earlier described principles, that are established in the Liberouter project, and it add some more features. All components of the verification environment are designed to be general and reusable, so they can be used also in other verifications related to the interconnection system. At the end of the thesis, there are discussed results of the verification, found bugs and the general advantages of simulation verifications.
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System of Internal Buses for Chips with FPGA Technology
Málek, Tomáš ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This thesis deals with design and implementation of interconnection bus system for chips with FPGA technology. The system ensures both communication between internal components on a chip and their communication with other computer elements which are mapped to the host system memory. The buses are high-speed, full duplex and packet-oriented and their architecture is based on tree topology. The data width is configurable, individually for every bus part. Due to this feature, it is possible to build uniform hierarchical system of internal buses with different speed that interconnects differently fast components. Proposed interconnection system was implemented in VHDL language and it is utilized in the Liberouter project which is the part of CESNET research intention Programable Hardware.
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Verification of FPGA Generic Interconnection System
Bartoš, Václav ; Martínek, Tomáš (referee) ; Puš, Viktor (advisor)
This thesis deals with design, implementation and realization of simulation verification of generic interconnection system for FPGA chips. This system is part of the NetCOPE platform developed in the Liberouter project, within which was this work done. In the beginning, an usual methods of verification in SystemVerilog language are described. Then there is a brief description of the interconnection system, aimed especially to aspects important to verification. The main part of the thesis is design of verification environment and control program of test for all three components of the tested system. It started form the earlier described principles, that are established in the Liberouter project, and it add some more features. All components of the verification environment are designed to be general and reusable, so they can be used also in other verifications related to the interconnection system. At the end of the thesis, there are discussed results of the verification, found bugs and the general advantages of simulation verifications.
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System of Internal Buses for Chips with FPGA Technology
Málek, Tomáš ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This thesis deals with design and implementation of interconnection bus system for chips with FPGA technology. The system ensures both communication between internal components on a chip and their communication with other computer elements which are mapped to the host system memory. The buses are high-speed, full duplex and packet-oriented and their architecture is based on tree topology. The data width is configurable, individually for every bus part. Due to this feature, it is possible to build uniform hierarchical system of internal buses with different speed that interconnects differently fast components. Proposed interconnection system was implemented in VHDL language and it is utilized in the Liberouter project which is the part of CESNET research intention Programable Hardware.
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