National Repository of Grey Literature 3 records found  Search took 0.01 seconds. 
Acceleration unit for HTTP headers identification in FPGA
Bryndza, Ivan ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
The bachelor thesis deals with hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. The goal is to design and implement a hardware architecture which will be used for detection of HTTP header in packet, and to achieve the throughput needed for monitoring of 100 Gbps networks. Nondeterministic finite automata and massive parallelism has been used for pattern match detection.
Acceleration unit for HTTP headers identification in FPGA
Bryndza, Ivan ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
The bachelor thesis deals with hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. The goal is to design and implement a hardware architecture which will be used for detection of HTTP header in packet, and to achieve the throughput needed for monitoring of 100 Gbps networks. Nondeterministic finite automata and massive parallelism has been used for pattern match detection.
Acceleration Unit for HTTP Headers Identification in FPGA
Bryndza, Ivan
This paper presents a hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. We have designed a hardware architecture, which will be used for detection of HTTP header in each packet. Architecture will be able to achieve the throughput needed for monitoring of 100 Gb/s networks. Nondeterministic finite automata and massive parallelism is used for pattern match.

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