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	Aproximace obvodů s využitím alternativních reprezentací Michalisko, Tomáš ; Mrázek, Vojtěch (referee) ; Sekanina, Lukáš (advisor) This master's thesis deals with the design of approximate circuits using alternative representations. The investigated representations include the And-inverter graph, Majority-Inverter graph, and Xor-Majority graph. Cartesian genetic programming is employed for design automation. By computing the approximation error using formal methods, the developed system can be applied to more complex circuits. In the first part of the experiments, the speed of the program is evaluated and optimized. Subsequently, a suitable mutation operator is searched for. Then, the system is tested for approximating 8-bit multipliers and 16-bit adders with the aim of minimizing size and delay. The results show that adders and multipliers in the XMG representation achieve better fitness values compared to evolution at the gate level. Finally, an evolution targeting the k-LUT technology is performed. Here, gates remain the most efficient representation. Detailed record
	Approximation of Digital Circuits in Yosys Tool Plevač, Lukáš ; Vašíček, Zdeněk (referee) ; Mrázek, Vojtěch (advisor) The goal of this work is introduction of cgploss extension. This extension is extension for combinational logic circuits optimization in Yosys tool. Cartesian genetic programming is introduced in the first part of this work. Cartesian genetic programming is a design and optimization method that can be used for circuit optimization and approximation. This chapter introduces representation of combinational logic circuits for Cartesian genetic programming. The next chapter introduces Yosys tool and possibilities of the Yosys extending. The proposed 'cgploss' extension is introduced in the next chapter. The chapter also provides details about the implementation and the usage. The last chapter tests cgploss extension and compares representation of combinational logic circuits. Detailed record
	Approximation of Digital Circuits in Yosys Tool Plevač, Lukáš ; Vašíček, Zdeněk (referee) ; Mrázek, Vojtěch (advisor) The goal of this work is introduction of cgploss extension. This extension is extension for combinational logic circuits optimization in Yosys tool. Cartesian genetic programming is introduced in the first part of this work. Cartesian genetic programming is a design and optimization method that can be used for circuit optimization and approximation. This chapter introduces representation of combinational logic circuits for Cartesian genetic programming. The next chapter introduces Yosys tool and possibilities of the Yosys extending. The proposed 'cgploss' extension is introduced in the next chapter. The chapter also provides details about the implementation and the usage. The last chapter tests cgploss extension and compares representation of combinational logic circuits. Detailed record

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