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Lattice-Based Cryptography on Constrained Devises
Shapoval, Vladyslav ; Dzurenda, Petr (referee) ; Ricci, Sara (advisor)
Tato diplomová práce prezentuje modifikovanou softwarovou implementaci podpisového schématu založeného na modulové mřížce Dilithium a jeho distribuované varianty DS2 pro mikrokontrolér ARM Cortex-M4. Dilithium je součástí sady CRYSTALS a byl vybrán NIST jako nový postkvantový podpisový standard. Tato práce se zaměřuje na snížení paměťové náročnosti obou algoritmů, aby byly více aplikovatelné na širší spektrum mikrokontrolérů a omezených zařízení. Oba podpisy byly optimalizovány pro běh na mikrokontroléru STM32 Cortex-M4. Na jedné straně Dilithium podpis prezentoval již optimalizovanou implementaci, která může běžet na mikrokontroléru. Proto jsme se zaměřili na přidání hardwarové akcelerace pro AES pro generování pseudonáhodných čísel během generování podpisu. Na druhé straně je podpis DS2 více paměťově náročný a navrhli jsme dva optimalizační přístupy přizpůsobené mikrokontroléru. Tyto optimalizace mají za cíl snížit spotřebu paměti při zachování bezpečnostní síly. Experimentální výsledky a bezpečnostní analýza demonstrují účinnost a praktičnost našich řešení. V důsledku naší práce jsme úspěšně vyvinuli nové verze jak Dilithium, tak DS2 s paměťovou spotřebou sníženou o více než 50\% a 90\%, respektive, ve srovnání s originálem.
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Postquantum cryptography on FPGA
Győri, Adam ; Jedlička, Petr (referee) ; Smékal, David (advisor)
This work describes the post-quantum algorithm FrodoKEM, its hardware implementation in VHDL and software simulation of implementation, subsequent implementation of the implementation on the FPGA process system. The work describes the issue of postquantum cryptography and VHDL programming language used to describe the functionality of hardware. Furthermore, the work deals with the functional implementation and simulation of all parts of the algorithm. Specifically, these are parts, key generation, encapsulation, and decapsulation. Algorithm implementation and simulations were performed in the Vivado software simulation environment, created by Xilinx. Subsequently, the synthesis and implementation was performed and the Intellectual property block was designed, the key part of which covered the functionality of the NEXYS A7 FPGA board was not available. The last part of the work deals with the workflow algorithm for implementation on FPGA board NEXYS A7.
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Post-quantum cryptography on constrained devices
Matula, Lukáš ; Dzurenda, Petr (referee) ; Malina, Lukáš (advisor)
In recent years, there has been a lot of technological development, which among other things, brings the designs and implementation of quantum computing. Using Shor’s algorithm for quantum computing, it is highly likely that the mathematical problems, which underlie the cryptographic systems, will be computed in polynomial time. Therefore, it is necessary to pay attention to the development of post-quantum cryptography, which is able to secure systems against quantum attacks. This work includes the summary and the comparison of different types of post-quantum cryptography, followed by measuring and analysing its levels of difficulty in order to implement them into limited devices, such as smart cards. The measured values on the PC are used to determine the most suitable implementation on the circuit card and then the verification method itself is implemented on it.
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Post Quantum Cryptography on FPGA
Gyõri, A. ; Smékal, D.
This work describes the post-quantum algorithm FrodoKEM, its hardware implementation in VHDL and software simulation of implementation. The issue of postquantum cryptography and the VHDL programming language used to describe the functionality of the hardware was studied. The acquired knowledge was transformed into a functional simulation of all parts of the algorithm. All these parts have already been implemented separately, so that the functionality of every single part can be separately approached. These parts are key generation, encapsulation and decapsulation. After successful simulation. These parts will be synthetised and implemented to FPGA board NEXYS A7.
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Postquantum cryptography on FPGA
Győri, Adam ; Jedlička, Petr (referee) ; Smékal, David (advisor)
This work describes the post-quantum algorithm FrodoKEM, its hardware implementation in VHDL and software simulation of implementation, subsequent implementation of the implementation on the FPGA process system. The work describes the issue of postquantum cryptography and VHDL programming language used to describe the functionality of hardware. Furthermore, the work deals with the functional implementation and simulation of all parts of the algorithm. Specifically, these are parts, key generation, encapsulation, and decapsulation. Algorithm implementation and simulations were performed in the Vivado software simulation environment, created by Xilinx. Subsequently, the synthesis and implementation was performed and the Intellectual property block was designed, the key part of which covered the functionality of the NEXYS A7 FPGA board was not available. The last part of the work deals with the workflow algorithm for implementation on FPGA board NEXYS A7.
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Post-quantum cryptography on constrained devices
Matula, Lukáš ; Dzurenda, Petr (referee) ; Malina, Lukáš (advisor)
In recent years, there has been a lot of technological development, which among other things, brings the designs and implementation of quantum computing. Using Shor’s algorithm for quantum computing, it is highly likely that the mathematical problems, which underlie the cryptographic systems, will be computed in polynomial time. Therefore, it is necessary to pay attention to the development of post-quantum cryptography, which is able to secure systems against quantum attacks. This work includes the summary and the comparison of different types of post-quantum cryptography, followed by measuring and analysing its levels of difficulty in order to implement them into limited devices, such as smart cards. The measured values on the PC are used to determine the most suitable implementation on the circuit card and then the verification method itself is implemented on it.
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