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Simulation of cryptographic algorithms using FPGA
Németh, František ; Mašek, Jan (referee) ; Smékal, David (advisor)
Bachelor thesis is dealing with a cipher standard AES and with a design of encryption and decryption components for AES in special modes of operation. Programming language is VHDL. In theoretical part of thesis is a further descriptions of AES and behaviour of block cipher operation modes. Furthermore the brief description of VHDL, FPGA and NetCOPE framework is a piece of theoretical part as well. The practical part contains designs which are made in developing environment Vivado from Xilinx. Programmed modes of operation are ECB, CBC, CTR and CFB. Simulation outputs and synthesis results are summerized in tables.
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Barcode recognition system
Pribula, Wojciech ; Richter, Miloslav (referee) ; Petyovský, Petr (advisor)
This thesis describes barcodes which are used in postal services. Specifically, it is concerned with Intelligent Mail Barcode, the GS1-128 code, the C128 code of Ceska posta (Czech Postal Services) and the QR code. The thesis attempts to analyze methods of encoding information into barcodes and error detection algorithms used for error correction during the decoding processes. Most importantly, there is described Reed-Solomon error correction in the QR code. There are presented and evaluated different methods of code detecting which are suggested by authors of various academic articles. The thesis also describes the method of creating test sets of images and proposed appearances of the scanning scene. Additionally, there are described algorithms for detection and decoding barcodes GS1-128, C128 and IMB in the image which was created during the work on this thesis. Finally, there is the evaluation of the percentage success of algorithms.
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Simulation of cryptographic algorithms using FPGA
Németh, František ; Mašek, Jan (referee) ; Smékal, David (advisor)
Bachelor thesis is dealing with a cipher standard AES and with a design of encryption and decryption components for AES in special modes of operation. Programming language is VHDL. In theoretical part of thesis is a further descriptions of AES and behaviour of block cipher operation modes. Furthermore the brief description of VHDL, FPGA and NetCOPE framework is a piece of theoretical part as well. The practical part contains designs which are made in developing environment Vivado from Xilinx. Programmed modes of operation are ECB, CBC, CTR and CFB. Simulation outputs and synthesis results are summerized in tables.
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Barcode recognition system
Pribula, Wojciech ; Richter, Miloslav (referee) ; Petyovský, Petr (advisor)
This thesis describes barcodes which are used in postal services. Specifically, it is concerned with Intelligent Mail Barcode, the GS1-128 code, the C128 code of Ceska posta (Czech Postal Services) and the QR code. The thesis attempts to analyze methods of encoding information into barcodes and error detection algorithms used for error correction during the decoding processes. Most importantly, there is described Reed-Solomon error correction in the QR code. There are presented and evaluated different methods of code detecting which are suggested by authors of various academic articles. The thesis also describes the method of creating test sets of images and proposed appearances of the scanning scene. Additionally, there are described algorithms for detection and decoding barcodes GS1-128, C128 and IMB in the image which was created during the work on this thesis. Finally, there is the evaluation of the percentage success of algorithms.
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