National Repository of Grey Literature 6 records found  Search took 0.01 seconds. 
Finite State Machines Generator Based on Graphics Definition for VHDL Language
Janyš, Martin ; Košař, Vlastimil (referee) ; Šimek, Václav (advisor)
The work introduces the reader to the possibilities of design and creation of nite state machines with focus on representation using VHDL. The main topic is the application that implements the VHDL code generator based on graphic description which can be create. The key application areas are described. In particular, their use and implementation that implements the actual transformation of the state diagram into VHDL.
Game for Oculus Quest
Kryštůfek, Jakub ; Novák, Jiří (referee) ; Pomikálek, Jiří (advisor)
The aim of this bachelor thesis is to create a prototype of a videogame in virtual reality for target platform Oculus Quest 2. The game was created with game engine Unity with emphasis on optimalization and extensibility of implemented systems. Within the implemented game was created system of autonomous agents via finite state machines and planning architecture goal-oriented action planning. One of the most insteresting game mechanics is fire propagation system implemented with cellular automaton.
Fast Regular Expression Matching Using FPGA
Kubiš, Juraj ; Fukač, Tomáš (referee) ; Matoušek, Denis (advisor)
Bachelor thesis deals with the possibility of hardware acceleration of regular expression matches. The content of the thesis is to analyze existing hardware architectures and evaluate their positive and negative properties. Based on this knowledge, the architecture is designed. It is based on deterministic finite automata with implicit transitions (D2FA), is implemented in VHDL and is synthesized. The synthesis results are analyzed to determine the overall throughput of the architecture. It is designed software to convert regular expressions into a D2FA and to optimize this automaton in order to minimize memory requirements. The implementation is verified and the benefits of individual optimization techniques to reduce memory requirements are evaluated.
Game for Oculus Quest
Kryštůfek, Jakub ; Novák, Jiří (referee) ; Pomikálek, Jiří (advisor)
The aim of this bachelor thesis is to create a prototype of a videogame in virtual reality for target platform Oculus Quest 2. The game was created with game engine Unity with emphasis on optimalization and extensibility of implemented systems. Within the implemented game was created system of autonomous agents via finite state machines and planning architecture goal-oriented action planning. One of the most insteresting game mechanics is fire propagation system implemented with cellular automaton.
Fast Regular Expression Matching Using FPGA
Kubiš, Juraj ; Fukač, Tomáš (referee) ; Matoušek, Denis (advisor)
Bachelor thesis deals with the possibility of hardware acceleration of regular expression matches. The content of the thesis is to analyze existing hardware architectures and evaluate their positive and negative properties. Based on this knowledge, the architecture is designed. It is based on deterministic finite automata with implicit transitions (D2FA), is implemented in VHDL and is synthesized. The synthesis results are analyzed to determine the overall throughput of the architecture. It is designed software to convert regular expressions into a D2FA and to optimize this automaton in order to minimize memory requirements. The implementation is verified and the benefits of individual optimization techniques to reduce memory requirements are evaluated.
Finite State Machines Generator Based on Graphics Definition for VHDL Language
Janyš, Martin ; Košař, Vlastimil (referee) ; Šimek, Václav (advisor)
The work introduces the reader to the possibilities of design and creation of nite state machines with focus on representation using VHDL. The main topic is the application that implements the VHDL code generator based on graphic description which can be create. The key application areas are described. In particular, their use and implementation that implements the actual transformation of the state diagram into VHDL.

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