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Development of an algorithm for optimizing clock balanced cells in a digital standard cell library
 Kříž, Lukáš ; Frýza, Tomáš (referee) ; Král, Vojtěch (advisor)
The bachelor thesis focuses on the analysis and optimization of clock-balanced cells in a digital standard library. The bachelor thesis was to explore the impact of cells in CMOS technology and assess their influence on the stability of the clock signal. Emphasis was placed on the effects of unbalanced clock cells in the path of the clock signal path, and the consequences that may arise if these cells are used. As part of the bachelor thesis, cells of logical operators such as buffer, inverter, AND, and OR were simulated. It is demonstrated how these cells are implemented in CMOS technology using PMOS and NMOS transistors, and the process of cell balancing is described. All simulations were conducted in the ngspice environment. Subsequently, the whole process was automated by developing an algorithm in Python.
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