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Graphical user interface for filter design
Tesařík, Jan ; Kledrowetz, Vilém (referee) ; Pristach, Marián (advisor)
This work deals with design of program that allows to generate VHDL description from connection of filters. Its main aim is to create graphical extension on existing program and connect it to VHDL generator. Output from program will be XML file of created connection and generated VHDL description. Design of program was done by using Qt Framework environment and C++ language.
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Design of digital decimation filter in CMOS technology
Toman, Petr ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
This Master’s thesis deals with digital decimation filter design for undersampling and filtering of sigma-delta ADC signal. Filter cascade is designed in Matlab according to given requirements and is then described in VHDL language aiming for minimum area. Implemented filter functionality is compared to Matlab-generated reference filters in created verification environment. Finally the design is synthesized in specified technology and verified on gate level.
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Software for digital filter verification
Tesařík, Jan ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
Diploma thesis deals with design of verification environment for analyzing systems with digital filters. Verification environment is written in SystemVerilog language and it is generated by program, which is also providing generation of input data for system of filters. Matlab environment is used for gaining the reference data. The simulation of the designed involvement with digital filters is performed by program ModelSim. The most watched parameter is functional coverage which indicates how big part of the HDL description has been tested.
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Marital process: Divorced Christians from the perspective of CIC
VÍTOVÁ, Marie
The work is focused on: 1. the practice of ecclesiastical courts operating on the territory of the Czech Republic in comparison with the practice of neighbouring countries, with respect to the motto proprio by Pope František Mitis Iudex Dominus Iesus from 2015; 2. Christians who have entered religious marriage, and who have passed or are now going through a marital crisis.
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Robotka's case
Skořepová, Michaela ; Čechurová, Jana (advisor) ; Plachý, Jiří (referee)
(in English): This thesis deals with post-war fate of Josef Robotka the member of the second and third resistence and people who cooperated with him. It cannot be mentioned his activities during the Second World War in the Council of three but the key issue will be the engagement after 1945. I would describe his disenchantment with communist ideas while on Vorošilov military academy in Moscow, subsequently forced to return to Czechoslovakia and post-February intelligence cooperation with CIC. I will also try to bring the role of public authorities in the arrest, detention and trial. In the next section I would like to map the entire arrest of Robotka group, their imprisonment and trial. The following chapters will deal with Robotka's execution and the role of wives and close relatives of convicted persons. The work is based mainly on archival research, supplemented by memories of Vlasta Nováčková Jakubová who is Robotka's niece and close collaborator. Main question is how big the importance of the information that the group sent abroad was and what significance should they have in case of possible conflict.
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Graphical user interface for filter design
Tesařík, Jan ; Kledrowetz, Vilém (referee) ; Pristach, Marián (advisor)
This work deals with design of program that allows to generate VHDL description from connection of filters. Its main aim is to create graphical extension on existing program and connect it to VHDL generator. Output from program will be XML file of created connection and generated VHDL description. Design of program was done by using Qt Framework environment and C++ language.
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Software for digital filter verification
Tesařík, Jan ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
Diploma thesis deals with design of verification environment for analyzing systems with digital filters. Verification environment is written in SystemVerilog language and it is generated by program, which is also providing generation of input data for system of filters. Matlab environment is used for gaining the reference data. The simulation of the designed involvement with digital filters is performed by program ModelSim. The most watched parameter is functional coverage which indicates how big part of the HDL description has been tested.
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Design of digital decimation filter in CMOS technology
Toman, Petr ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
This Master’s thesis deals with digital decimation filter design for undersampling and filtering of sigma-delta ADC signal. Filter cascade is designed in Matlab according to given requirements and is then described in VHDL language aiming for minimum area. Implemented filter functionality is compared to Matlab-generated reference filters in created verification environment. Finally the design is synthesized in specified technology and verified on gate level.
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