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Spread of delay on railway network
Straka, Martin ; Babilon, Robert (advisor) ; Libič, Peter (referee)
The subject of this work is a simulation of late trains spreading in railway net. This program shows the single simulations and creates their statistics according to different criteria (for example changing waiting periods or changes in crossing of the trains). This work evaluates and compares the results. Next point of this work is an effort to suggest the most appropriate criteria in order to prevent the train lag. Another element of this work includes searching for weak points in grafikon, which includes the trains that are late more frequently than other or do not wait for an arrival of the previous ones on their way because of the great lag.
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Using Neural Networks in the Hierachical Routing
Straka, Martin ; Lokoč, Jakub (referee) ; Štanclová, Jana (advisor)
The objective of the diploma thesis is to show possible utilization of the neural networks for the partitioning needs of the hierarchical routing algorithm. The work proposes a hierarchical approach, which can be useful for the optimal path searching process. We focus on the application of several neural network models to extract hierarchical information from the transportation network data. Introduced models are based on the energy minimization principle and we demonstrate an employment of the deterministic annealing methods (MFA) as quite ambitious in the partitioning process. The experimental part of this work makes use of our findings and propose several suggestions on the proper parametrization of employed neural network models. In the experimental tests, we demonstrate capabilities of the MFA to provide a partitioning task also in case of lack of the global information.
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Spread of delay on railway network
Straka, Martin ; Babilon, Robert (advisor) ; Pergel, Martin (referee)
The subject of this work is a simulation of late trains spreading in railway net. This program shows the single simulations and creates their statistics according to different criteria (for example changing waiting periods or changes in crossing of the trains). This work evaluates and compares the results. Next point of this work is an effort to suggest the most appropriate criteria in order to prevent the train lag. Another element of this work includes searching for weak points in grafikon, which includes the trains that are late more frequently than other or do not wait for an arrival of the previous ones on their way because of the great lag.
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Methodology of highly reliable systems design
Straka, Martin ; Gramatová, Elena (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Methodology of highly reliable systems design
Straka, Martin ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Data Acquisition from HTML Sites
Komenda, Tomáš ; Šimek, Václav (referee) ; Straka, Martin (advisor)
This work describes scope of creating application for extraction and following data from HTML sites. This work engages in lexical analyze and parsing HTML. This work describes filtration of data from HTML sites. This work describes saving of data in database and XML documents, creating of dynamic HTMP pages, timer cron, GNU utility wget, sending of SMS, sending email and extraction of date from internet. Final chapters describe two web applications. These applications follow data from HTML sites and inform users about changes.
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Evolution Algorithm Used in Chess Game
Urminský, Andrej ; Straka, Martin (referee) ; Gajda, Zbyšek (advisor)
This thesis deals with a design of an evolutionary algorithm for an artificial intelligence in a chess game. This is accomplished by use of so called genetic algorithms. Java programming language and Eclipse, an open development platform, were used for implementation of this algorithm and the graphical user interface.
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Car Air-Condition Control Unit with MCU HCS08GT60
Polóni, Pavol ; Straka, Martin (referee) ; Šimek, Václav (advisor)
The purpose of this project is to desing and produce development board, which is customized with respect to the deployment as an air-condition control unit in car. The following chapters of this work will gradually take its reader through the whole design flow of such embedded system. Literally speaking, selection of a proper MCU and set of external peripherals can be seen as the critical tasks. Particular attention will be also given to PCB (printed circuit board) manufacturing and components assembly. The core of the system is built around HCS08 MCU from Freescale and appropriate firmware written in C language.
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Electronic Management of Agility Race
Vorlová, Pavla ; Straka, Martin (referee) ; Kaštil, Jan (advisor)
The work describes implementation of system for agility competition manegement. The system contains web interface and program which evaluates results in competition location. This thesis describes usage of JSP, Java Beans and MySQL. The focus was on transfering data between web database and client application database.
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