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Methodology of highly reliable systems design
Straka, Martin ; Gramatová, Elena (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Physically-based Modeling and Simulation
Dvořák, Radim ; Racek, Stanislav (referee) ; Šujanský,, Milan (referee) ; Zbořil, František (advisor)
Disertační práce se zabývá modelováním znečištění ovzduší, jeho transportních a disperzních procesů ve spodní části atmosféry a zejména numerickými metodami, které slouží k řešení těchto modelů. Modelování znečištění ovzduší je velmi důležité pro předpověď kontaminace a pomáhá porozumět samotnému procesu a eliminaci následků. Hlavním tématem práce jsou metody pro řešení modelů popsaných parciálními diferenciálními rovnicemi, přesněji advekčně-difúzní rovnicí. Polovina práce je zaměřena na známou metodu přímek a je zde ukázáno, že tato metoda je vhodná k řešení určitých konkrétních problémů. Dále bylo navrženo a otestováno řešení paralelizace metody přímek, jež ukazuje, že metoda má velký potenciál pro akceleraci na současných grafických kartách a tím pádem i zvětšení přesnosti výpočtu. Druhá polovina práce se zabývá poměrně mladou metodou ELLAM a její aplikací pro řešení atmosférických advekčně-difúzních rovnic. Byla otestována konkrétní forma metody ELLAM společně s navrženými adaptacemi. Z výsledků je zřejmé, že v mnoha případech ELLAM překonává současné používané metody.
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Application of infrared spectrometry in the activities of Fire Rescue Brigade
Racek, Stanislav ; Vávrová, Milada (referee) ; Čáslavský, Josef (advisor)
This diploma work is aimed at the use of infrared spectrometry by Fire Brigade Units of the Czech Republic. A new portable instrument True Defender FT produced by Ahura was used for this purpose. It was lent by the Institute of Citizens´Protection in Lázně Bohdaneč. The goal of this work is to get acquainted with this instrument and to evaluate its ability to identify unknown substances. Experimental part was aimed at the testing of this spectrometer with the help of model sample set, containing samples from real situations solved by members of Fire Brigade Units of the Czech Republic. Possibilities of mobile infrared spectometer True Defender FT and mobile Raman spectometer First Defender are finally compared.
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Methodology for Fault Tolerant Systems Design into Limited Implementation Area in FPGA
Mičulka, Lukáš ; Racek, Stanislav (referee) ; Vlček, Karel (referee) ; Kotásek, Zdeněk (advisor)
Tato práce popisuje navrženou metodologii pro návrh systémů odolných proti poruchám v FPGA schopnou ochránit systém před projevy přechodných a trvalých poruch. Oprava přechodné poruchy je prováděna částečnou dynamickou rekonfigurací. Oprava omezeného počtu trvalých poruch je založena na použití odolných architektur využívajících menší množství zdrojů než předchozí použitá architektura. Vadná část FPGA tak není dále využívána. Tato technika je založena na použití předkompilovaných konfigurací uložených v externí paměti. Pro snížení paměťových nároků pro uložení konfiguračních bitových posloupností je použita technika relokace.
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Methodology for fault tolerant system state synchronization design and its recovery from faults
Szurman, Karel ; Fišer, Petr (referee) ; Racek, Stanislav (referee) ; Vlček, Karel (referee) ; Kotásek, Zdeněk (advisor)
In this Ph.D. thesis, a new methodology for the fault tolerant system state synchronization design and its recovery from faults is presented. A state synchronization method designed by means of the proposed methodology allows to repair the state of sequential logic elements implemented in the FPGA application logic, which cannot be repaired by the partial dynamic reconfiguration. The proposed methodology describes possible state synchronization design methods with respect to TMR granularity, dependence of the system function on its previous states and the system architecture. The methodology focuses on coarse-grained TMR architectures and state synchronization in the systems controlled by means of finite state machines or a processor. The use of the methodology is demonstrated on the CAN bus control system and the microcontroller NEO430, for which specific synchronization methods were designed. The systems reliability and new ability of the systems for recovery from faults were verified in the presence of simulated SEU faults. The experimental results and the contribution of this thesis are discussed in the conclusion.
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Test Application Methodology Based On the Identification of Testable blocks
Herrman, Tomáš ; Plíva, Zdeněk (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
The PhD thesis deals with the analysis of digital systems described on RT level. The methodology of data paths analysis is decribed, the data path controller analysis is not solved in the thesis. The methodology is built on the concept of Testable Block (TB) which allows to divide digital component to such segments which can be tested through their inputs/outputs, border registers and primary inputs/outputs are used for this purpose. As a result, lower number of registers is needed to be included into scan chain - border registers are the only ones which are scanned. The segmentation allows also to reduce the volume of test vectors, tests are generated for segments, not for the complete component. To identify TBs, two evolutionary algorithms are used, they operate on TB formal model which is also defined in the thesis.
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Variability of Execution Environments for Component-based Systems
Malohlava, Michal ; Bureš, Tomáš (advisor) ; Racek, Stanislav (referee) ; Duchien, Laurence (referee)
Reuse is considered as one of the most crucial software engineering concerns. It allows for delivering software systems faster with less effort. Therefore, the thesis explores limits of reuse in the context of component systems. It analyzes in depth contemporary component systems, finds their commonalities and variation points, and introduces a meta-component system -- a software product line which allows for producing a tailored component system based on a set of requirements. The thesis addresses the meta-component system definition and focuses on its crucial aspects which play the key role in component systems preparation- (1) a configurable execution environment and (2) generation of implementation artifacts. To address the first aspect, the thesis proposes a model-driven method for creating configurable execution environments. Motivated by creating execution environments, the thesis contributes to (2) by introducing a notion of domain-specific languages interoperability in the context of the code generation. Furthermore, the thesis elaborates the proposed notion resulting into a family of interoperable domain-specific languages which is parametrized by a general purpose language.
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Methodology for fault tolerant system state synchronization design and its recovery from faults
Szurman, Karel ; Fišer, Petr (referee) ; Racek, Stanislav (referee) ; Vlček, Karel (referee) ; Kotásek, Zdeněk (advisor)
In this Ph.D. thesis, a new methodology for the fault tolerant system state synchronization design and its recovery from faults is presented. A state synchronization method designed by means of the proposed methodology allows to repair the state of sequential logic elements implemented in the FPGA application logic, which cannot be repaired by the partial dynamic reconfiguration. The proposed methodology describes possible state synchronization design methods with respect to TMR granularity, dependence of the system function on its previous states and the system architecture. The methodology focuses on coarse-grained TMR architectures and state synchronization in the systems controlled by means of finite state machines or a processor. The use of the methodology is demonstrated on the CAN bus control system and the microcontroller NEO430, for which specific synchronization methods were designed. The systems reliability and new ability of the systems for recovery from faults were verified in the presence of simulated SEU faults. The experimental results and the contribution of this thesis are discussed in the conclusion.
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Methodology for Fault Tolerant Systems Design into Limited Implementation Area in FPGA
Mičulka, Lukáš ; Racek, Stanislav (referee) ; Vlček, Karel (referee) ; Kotásek, Zdeněk (advisor)
Tato práce popisuje navrženou metodologii pro návrh systémů odolných proti poruchám v FPGA schopnou ochránit systém před projevy přechodných a trvalých poruch. Oprava přechodné poruchy je prováděna částečnou dynamickou rekonfigurací. Oprava omezeného počtu trvalých poruch je založena na použití odolných architektur využívajících menší množství zdrojů než předchozí použitá architektura. Vadná část FPGA tak není dále využívána. Tato technika je založena na použití předkompilovaných konfigurací uložených v externí paměti. Pro snížení paměťových nároků pro uložení konfiguračních bitových posloupností je použita technika relokace.
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