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Processing Unit for Analysis and Modification of Network Traffic
Pazdera, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This paper deals with the design and implementation of the Processing Unit for Analysis and Modification of Network Traffic. The proposed unit is intended to analyse an incoming network traffic and perform packet header editations to provide the proper packet delivery. The designed architecture has the following characteristics. It is based on the stream processor concept which allows to process independent stream elements (i.e. packets) in parallel. Multiply stream clients can be used to process the same stream data concurrently. The stream clients can be driven either autonomously or by program. The packets are processed according to the incoming metadata and transmited to the output. The Processing Unit has been implemented in VHDL language. The target technology is Field Programmable Gate Array (FPGA).
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Efficiency Analysis of the Business Project
Furchová, Hana ; Pazdera, Jan (referee) ; Žižlavský, Ondřej (advisor)
The master‘s thesis is focused on the economic efficiency analysis of business project of construction of harvest lines specific company. The work is used to evaluation of financial health, Porter’s five forces model, PEST and SWOT analysis, planning cash flows from the project and creation of variants for different operating conditions. To assess the suitability of the investment was used static and dynamic methods and risk analysis. The thesis includes recommendations to decision of investment.
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Processing Unit for Analysis and Modification of Network Traffic
Pazdera, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This paper deals with the design and implementation of the Processing Unit for Analysis and Modification of Network Traffic. The proposed unit is intended to analyse an incoming network traffic and perform packet header editations to provide the proper packet delivery. The designed architecture has the following characteristics. It is based on the stream processor concept which allows to process independent stream elements (i.e. packets) in parallel. Multiply stream clients can be used to process the same stream data concurrently. The stream clients can be driven either autonomously or by program. The packets are processed according to the incoming metadata and transmited to the output. The Processing Unit has been implemented in VHDL language. The target technology is Field Programmable Gate Array (FPGA).
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|
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Efficiency Analysis of the Business Project
Furchová, Hana ; Pazdera, Jan (referee) ; Žižlavský, Ondřej (advisor)
The master‘s thesis is focused on the economic efficiency analysis of business project of construction of harvest lines specific company. The work is used to evaluation of financial health, Porter’s five forces model, PEST and SWOT analysis, planning cash flows from the project and creation of variants for different operating conditions. To assess the suitability of the investment was used static and dynamic methods and risk analysis. The thesis includes recommendations to decision of investment.
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