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Generation of Binary Prefix Tree According to Probabilistic Parameters
Ženčák, Tomáš ; Kučera, Jan (referee) ; Matoušek, Jiří (advisor)
The goal of this work is to create a prefix set generator which will be capable of generating a prefix set from parameters specified in the ClassBench toolset. This work describes a possible approach to generation, as well as the final algorithm for prefix set generation. The resulting generator is able to generate prefix sets whose average deviation from the target parameters is typically orders of magnitude lower than the deviation of sets generated by ClassBench.
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Network Traffic Simulation and Generation
Matoušek, Jiří ; Kořenek, Jan (referee) ; Korček, Pavol (advisor)
Development of computer networks able to operate at the speed of 10 Gb/s imposes new requirements on newly developed network devices and also on a process of their testing. Such devices are tested by replaying synthetic or previously captured network traffic on an input link of the tested device. We must be able to perform both tasks also at full wire speed. Current testing devices are either not able to operate at the speed of 10 Gb/s or they are too expensive. Therefore, the aim of this thesis is to design and implement a hardware accelerated application able to generate and replay network traffic at the speed of 10 Gb/s. The application is accelerated in the FPGA of the COMBOv2 card and it also utilizes the NetCOPE platform. Architecture of the application is modular, which allows easy implementation of different modes of operation. The application implements both capturing and replaying network traffic at full wire speed, but traffic can be limited to a specified value of bitrate at the output. The thesis is concluded by a comparison of the implemented application and the packet generator implemented on the NetFPGA platform. According to this comparison, the implemented application is better than the NetFPGA packet generator.
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Development of Simulation Models of P4 Language
Bulička, Miroslav ; Matoušek, Jiří (referee) ; Martínek, Tomáš (advisor)
CESNET association is developing tool that allows running P4 programs on field programmable gate array. This tool is used in design of digital circuit, which goes through verification process. The verification uses behavioral model, which does not fully meet requirements. This thesis deals with introduction to P4 language, creation of behavioral models and developing of behavioral model, which meets the requirements of CESNET association. Current behavioral model, used in verification process, will be replaced by developed model. Project Behavioral Model version 2 was used for developing of behavioral model. Behavioral model simple switch was used as default model. This model is edited based on requirements of CESNET association. Result of this thesis is behavioral model which meets the requirements.
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Modelling and behaviour of composite systems in AC electric field
Matoušek, Jiří ; Frk, Martin (referee) ; Rozsívalová, Zdenka (advisor)
This work deals with modeling of progression of dielectric variables and mixture formulas for solution of properties of composite materials in dependency on frequency. Theoretical part of the work explains physical principles of polarisation mechanisms and influence on dielectric constant with changing temperature and frequency. In theoretical part processes inside the composite material, which is in electrical field are described. The work contains summary of mixture formulas and methods of their derivation. Program for use in education is a part of the work. It allows modelling of progression of dielectric variables in dependency on frequency and Cole-Cole circle diagram. In mixtures it allows modelling of frequency dependencies of dielectric constant in accordance to Maxwell's, Bőttcher's and Lichtenecker's mixture formulas.
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High-Speed Packet Data DMA Transfers to FPGA
Kubálek, Jan ; Matoušek, Jiří (referee) ; Martínek, Tomáš (advisor)
This thesis deals on the design, implementation, testing and measuring of a firmware module for FPGA chips, which enables DMA transfers of network data from computer RAM to the FPGA chip placed on a network interface card. These transfers are carried out using a PCIe bus on the speed of up to 100 Gbps with the possible support of speeds 200 Gbps and 400 Gbps. The goal of this technology is to allow network data processing for the purpose of maintenance of backbone network nodes and data centers. The module is designed so it can be used on different types of FPGA chips, mainly those produced by companies Xilinx and Intel.
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IPv6 Prefix Sets Generator
Utkin, Kirill ; Kučera, Jan (referee) ; Matoušek, Jiří (advisor)
Due to the fast adoption of IPv6 protocol, number of IPv6 prefixes in routing tables are incessantly increasing. Based on this fact, development of new lookup algorithms is required. However, testing of those algorithms is highly dependent on size of datasets, which are not large enough for this purpose at the moment. Design and implementation of generator of IPv6 prefix sets, which will be based on currently using address allocation policies, is the main goal of this bachelor's thesis. Implementation of generator was preceded by study and implementation of the generator V6Gene. Validation of generated datasets were performed by comparing length distribution and level distribution of prefixes with the real world datasets. Finally, speed of the generating process and memory usage were compared for implemented generators.
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Fast Generator of Network Flows
Budiský, Jakub ; Dvořák, Milan (referee) ; Matoušek, Jiří (advisor)
Tato diplomová práce se věnuje analýze existujících řešení pro generování síťového provozu určeného k testování síťových komponent. Zaměřuje se na generátory na úrovni IP síťových toků a pokrývá návrh a implementaci generátoru, zvaného FLOR, schopného vytvářet syntetický síťový provoz rychlostí až několik desítek gigabitů za sekundu. K plánování toků využívá náhodného procesu. Vytvořená aplikace je otestována a porovnána s existujícími nástroji. V závěru jsou navrženy další vylepšení a optimalizace.
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Measuring Parameters of Communication over PCI Express
Matějka, Martin ; Martínek, Tomáš (referee) ; Matoušek, Jiří (advisor)
This bachelor thesis describes designing a unit capable of measuring throughput on a PCI Express bus. The described unit is designed for an FPGA chip on an acceleration card with PCI Express 3.0 interface. At the same time, the thesis describes software implemented in C language used for its control. In the last section of this bachelor thesis are experiments conducted with the designed and implemented unit.
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Comparison of IPv6 Prefix Set Generators
Vašek, Dominik ; Kučera, Jan (referee) ; Matoušek, Jiří (advisor)
This bachelor's thesis aims to compare the IPv6 generators. In the first part we introduce protocol IPv6 and the allocation policies of registrars in order to better understand the problem. Next, we introduce three existing prefix set generators, whose description is available. In the second part of the thesis we propose and implement a series of tests for the prefix set generators. Lastly, we test the generators and make a conclusion based on the results. According to our results, we conclude that the prefix sets from the NonRandom and IPv6Table generators have a large error in comparison with a target prefix set. However, V6Gene, the implementation of which is not currently publicly available, might generate prefix sets close to the reality based on its proposal.
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