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Hardware Acceleration of Encryption Algorithms Using Xilinx Zynq Technology
Linner, Marek ; Fukač, Tomáš (referee) ; Kořenek, Jan (advisor)
The main concern of this paper are two world standard encryption algorithms Data Encryption Standard DES (DES for short) and Advanced Encryption Standard (further mentioned as AES). For these two respective algorithms, three publicly available implementations are integrated into a benchmarking code in C programming language. The code has been executed, implementations measured with three different input block lengths and bitrate calculated for each implementation. The thesis also includes hardware implementation of both encryption algorithms DES and AES using VHDL language, simulation of the synthesised circuits and calculation of the hardware implementations' bitrate using Vivado simulator's timing reports. These measured bitrates are then compared with the bitrates of benchmarked software implementations. Paper includes all source codes of the benchmarking C program and VHDL implementation, along with program written in C# used to generate VHDL components and another C# program used for automated testing.
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Implementation of Encryption Algorithms in VHDL Language
Fruněk, Lukáš ; Fukač, Tomáš (referee) ; Kořenek, Jan (advisor)
The thesis deals with the design and implementation of the encryption algorithms DES and AES, operating in the CTR mode. The designed modules are implemented in the VHDL language and are mapped in the FPGA Intel Arria 10 SX 480. Algorithms are optimized for maximum throughput using loop unrolling and inner pipelining. The encryption module for DES reaches throughput of 26.2 Gbit/s with the circuit operating 410 MHz, and the module for AES reaches throughput of 34.6 Gbit/s with the circuit operating at 271 MHz. The reached throughput is in the order of thousand times faster than of the same encryption algorithms implemented in software for built-in microprocessors.
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Flexible Load Balancer Using P4 Language
Šesták, Jindřich ; Fukač, Tomáš (referee) ; Martínek, Tomáš (advisor)
Currently servers of internet services are usually grouped together into clusters to provide sufficient performance to serve clients' queries. Each cluster needs Load Balancer, so it can choose one server which will process query from one client. For describing such device that processes packets is convenient to use P4 language. Within this work, the principles of load balancing, design, implementation and testing of a simple Load Balancer described in P4 language were demonstrated. The program is tested using Behavioral model of P4 language on a common processor and on the NFB-200G2QL card thanks to the Netcope environment from the CESNET association
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Protection Against DoS Attacks Using P4 Language
Vojanec, Kamil ; Fukač, Tomáš (referee) ; Kučera, Jan (advisor)
This thesis focuses on reimplementation of existing DoS (Denial of Service) attack mitigation device with high-level P4 programming language. The main reason for using P4 is to enhance adaptability and functionality to different types of DoS attacks. The created device is designed in a modular way and enables easy alterations by using interchangeable components. The target platform for this thesis is an FPGA acceleration card. The work results in designing several DoS mitigation components and implementing applications composed of these components. Pats of this work have been presented at IEEE ANCS (Symposium on Architectures for Networking and Communication Systems) in September 2019 at University of Cambridge.
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System for the Protection against DoS Attacks Using IDS
Mjasojedov, Igor ; Fukač, Tomáš (referee) ; Kučera, Jan (advisor)
This bachelor's thesis deals with the use of the Intrusion Detection System in the protection of computer networks against Denial of Service attacks. Suricata is the IDS system chosen for this purpose. The main goal of the thesis is to integrate the Suricata system with the DDoS Protector device. DDoS Protector - DCPro is a security network device, which uses, from a software perspective, DPDK technology for high-speed network traffic processing. Due to this fact, this technology was also integrated into the Suricata system. After this integration, the communication between DDoS Protector and Suricata system was allowed more easily. As a result, two DPDK compatible regimes were created in the Suricata system. The individual regime allows Suricata to process network data directly from the network interface card. The second, integrated regime allows DCPro to send network data to the Suricata system for highly precise analysis, which significantly extends DDoS Protector's attack detection abilities.
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DPDK Accelerated Firewall
Holubář, Jiří ; Fukač, Tomáš (referee) ; Vrána, Roman (advisor)
Nowadays, when almost everyone uses the Internet, network traffic security must also be ensured. This is what firewall helps with. Some routes require higher bandwidth than others. This thesis explores possibilities of using the DPDK library when implementing the firewall in order to achieve the highest possible bandwidth.
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Microprobe on the Xilinx Zynq Platform
Fukač, Tomáš ; Korček, Pavol (referee) ; Viktorin, Jan (advisor)
This work describes portation of microprobe firmware to Xilinx Zynq platform. Based on the study of the target platform of board ZE7000 was created a draft of firmware. RSoC Framework provides interconnections between programmable logic (FPGA) and operating system. With this framework we can find an abstract and universal way to develop applications that are accelerated in the FPGA and running in Linux operating system.
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Fast Regular Expression Matching Using FPGA
Kubiš, Juraj ; Fukač, Tomáš (referee) ; Matoušek, Denis (advisor)
Bachelor thesis deals with the possibility of hardware acceleration of regular expression matches. The content of the thesis is to analyze existing hardware architectures and evaluate their positive and negative properties. Based on this knowledge, the architecture is designed. It is based on deterministic finite automata with implicit transitions (D2FA), is implemented in VHDL and is synthesized. The synthesis results are analyzed to determine the overall throughput of the architecture. It is designed software to convert regular expressions into a D2FA and to optimize this automaton in order to minimize memory requirements. The implementation is verified and the benefits of individual optimization techniques to reduce memory requirements are evaluated.
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Traffic Shaping in High Speed Networks in DPDK
Doležal, Pavel ; Fukač, Tomáš (referee) ; Vrána, Roman (advisor)
This bachelor thesis is focused on traffic shaping in high speed networks. It presents framework DPDK, which can be used for fast packet processing. General traffic shaping mechanisms are described as well as traffic shaping in Linux using program tc. It also introduces a design and implementation of traffic shaper using DPDK framework for networks with 10 Gbps bandwidth. The traffic shaper uses a complex mechanism of hierarchical token bucket. The system was tested using high speed traffic generator Spirent.
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Probe for the Application Protocols Monitoring
Fukač, Tomáš ; Košař, Vlastimil (referee) ; Viktorin, Jan (advisor)
This work describes an extension of the Microprobe functionality for detection and filtering of application protocols. The Microprobe is an embedded system designed for monitoring network links at speed 1 Gb/s without loosing any packets. The detection of application protocols requires using of computationally expensive operations, especially string lookup (usually based on regular expressions). Based on the study of several protocols (SMTP, POP3, FTP, SIP) a draft of a new architecture has been created. The new architecture splits this functionality between programmable logic FPGA and processor. The FPGA performs preprocessing of network traffic consisting of a lookup for user identifiers and protocol-specific patterns. The processor verifies that it is the requested communication. The processor does not need to process the entire network traffic but only the part pre-filtered in the FPGA. The software part is extended by a module for the analysis of SMTP which allows processing of more than 5,000 network flows per second. Support for other protocols can be added by an extension of the software part.
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