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National Repository of Grey Literature 4 records found  Search took 0.01 seconds. 
Implementation of fast serial bus on FPGA
 Drbal, Jakub ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources.
Detailed record
Graphical interface for industrial display in gate array
 Drbal, Jakub ; Macháň, Ladislav (referee) ; Pristach, Marián (advisor)
This Bachelor’s thesis deals with design and realization of graphic interface that allows rendering of characters and basic text formatting on the industrial display. This interface is designed for Spartan 3 gate array. Comunication with superior system is through serial interface. Design is separated into five parts in order to achieve easier modification of the design. The thesis also deals with design of expansion board for display connection with the development kit and design of demonstration boar for realized interfaces.
Detailed record
Graphical interface for industrial display in gate array
 Drbal, Jakub ; Macháň, Ladislav (referee) ; Pristach, Marián (advisor)
This Bachelor’s thesis deals with design and realization of graphic interface that allows rendering of characters and basic text formatting on the industrial display. This interface is designed for Spartan 3 gate array. Comunication with superior system is through serial interface. Design is separated into five parts in order to achieve easier modification of the design. The thesis also deals with design of expansion board for display connection with the development kit and design of demonstration boar for realized interfaces.
Detailed record
Implementation of fast serial bus on FPGA
 Drbal, Jakub ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources.
Detailed record

See also: similar author names
1 Drbal, Jan
4 Drbal, Jaroslav
4 Drbal, Jindřich
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