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A Hardware-acceleration Protocol Design for Demanding Computations over Multiple Cores
Bareš, Jan ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This work deals with design of communication protocol for data transmission between control computer and computing cores implemented on FPGA chips. The purpose of the communication is speeding the performance demanding software algorithms of non-stream data processing by their hardware computation on accelerating system. The work defines a terminology used for protocol design and analyses current solutions of given issue. After that the work designs structure of the accelerating system and communication protocol. In the main part the work describes the implementation of the protocol in VHDL language and the simulation of implemented modules. At the end of the work the aplication of designed solution is presented along with possible extension of this work.
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An Encoder and Decoder of an Error-correction Code for Programmable Read-only Memories
Bareš, Jan ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This work deals with theory of coding, analyses current groups of error correction codes and describes features and parametres of chosen representatives of these groups. By comparing these parametres along with given criteria it choses extended Hamming code as suitable code for securing read-only-memories (ROM). For this code it choses way of realization of synthetisable modules of coder and decoder and describes their design. The work describes design of synthetizable modules of coder and decoder in VHDL. Then it explains functionality of created application which is able to generate these synthetisable modules. For verification of generated modules it creates authentication environment. Part of this environment is also model of ROM allowing writing of any error value into the memory. In the end it automatically verifies generated modules of coder and decoder with various width of input information vector.
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A Hardware-acceleration Protocol Design for Demanding Computations over Multiple Cores
Bareš, Jan ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This work deals with design of communication protocol for data transmission between control computer and computing cores implemented on FPGA chips. The purpose of the communication is speeding the performance demanding software algorithms of non-stream data processing by their hardware computation on accelerating system. The work defines a terminology used for protocol design and analyses current solutions of given issue. After that the work designs structure of the accelerating system and communication protocol. In the main part the work describes the implementation of the protocol in VHDL language and the simulation of implemented modules. At the end of the work the aplication of designed solution is presented along with possible extension of this work.
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An Encoder and Decoder of an Error-correction Code for Programmable Read-only Memories
Bareš, Jan ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This work deals with theory of coding, analyses current groups of error correction codes and describes features and parametres of chosen representatives of these groups. By comparing these parametres along with given criteria it choses extended Hamming code as suitable code for securing read-only-memories (ROM). For this code it choses way of realization of synthetisable modules of coder and decoder and describes their design. The work describes design of synthetizable modules of coder and decoder in VHDL. Then it explains functionality of created application which is able to generate these synthetisable modules. For verification of generated modules it creates authentication environment. Part of this environment is also model of ROM allowing writing of any error value into the memory. In the end it automatically verifies generated modules of coder and decoder with various width of input information vector.
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