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National Repository of Grey Literature

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	Platforma pro rychlý vývoj rekonfigurovatelného zpracování obrazu Kovář, Bohumil ; Kloub, Jan ; Schier, Jan ; Heřmánek, Antonín This paper outlines a proposed architecture for an integrated partial rapid prototyping dynamic reconfigurable system-on-a-chip, targeted at embedded real-time video and image processing. Detailed record
	Compression Algorithms and Their Implementation Kovář, Bohumil ; Schier, Jan The review of basic image compression methods is presented. The algorithms are evaluated regarding to benchmark software CBench. Detailed record
	Important points detection in a integral edge map Kovář, Bohumil The research report contains comparison of computational efficient algorithm for corner detection in a images with traditional approaches. Detailed record
	Konvertor Simulinkových modelů pro vestavěný videoakcelerátor Kovář, Bohumil ; Schier, Jan ; Zemčík, P. ; Herout, A. ; Zuzaňák, J. An embedded DSP/FPGA system for accelaration of image or video processing, with a scripting-language-based configuration engine, pulling software modules or hardware blocks from function libraries, is considered. The Simulink environment is used for rapid application design for this system. The aspects of converting Simulink block diagrams into the scripting language for the configuration engine are discussed in the paper. Detailed record
	Simulink jako nástroj pro vývoj rekonfigurovatelných aplikací Kovář, Bohumil ; Schier, Jan ; Zemčík, P. ; Herout, A. ; Beran, V. Our paper focuses on rapid prototyping and configuration tools for an embedded system. It will present novel concept of an image processing architecture based on interconnection of a programmable logical chip (FPGAs) with digital signal processor (DSP). In the paper, we shall outline a configuration tool tailored towards systems combining both DSP and FPGA, based on a configuration/programming scripting language and with a complex library of functions and modules for selected applications in signal and video processing. Detailed record
	Rekonfigurovatelná architektura pro zpracování obrazu s podporou rychlého modelování v Simulinku Schier, Jan ; Kovář, Bohumil ; Zemčík, P. ; Herout, A. ; Beran, V. A novel concept of an embedded image processing architecture is presented in the paper. This architecture is based on an interconnection of a programmable logical chip with a digital signal processor. Both these devices have characteristic that complement well each other for broad-class of data-intensive image-and video-processing tasks. For efficient utilization of such device, a multi-level configuration system is needed. The paper describes both the HW and SW architecture of the system. Detailed record

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