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Automatic Construction of Checking Circuits Based on Finite Automata
 Matušová, Lucie ; Strnadel, Josef (oponent) ; Kaštil, Jan (vedoucí práce)
The aim of this thesis was to study active automata learning, to design and implement a software architecture for the automatic construction of a checking circuit for a given unit implemented in FPGA, and to verify the functionality of the checking circuit by fault injection. The checking circuit, denoted as an online checker, introduces fault tolerance aspects to the unit. The checker is constructed from a model inferred by active automata learning, which is based on communication with a simulator. To implement the learning environment, LearnLib library has been employed. It provides active automata learning algorithms and their optimizations. An experimental platform enabling controlled fault injection into a design in FPGA was designed and implemented. The platform was used to test the capabilities of the obtained checker. The experimental results show that the error rate is reduced by more than 98% if the checker and reconfiguration is used.
Úplný záznam
Automatic Construction of Checking Circuits Based on Finite Automata
 Matušová, Lucie ; Strnadel, Josef (oponent) ; Kaštil, Jan (vedoucí práce)
The aim of this thesis was to study active automata learning, to design and implement a software architecture for the automatic construction of a checking circuit for a given unit implemented in FPGA, and to verify the functionality of the checking circuit by fault injection. The checking circuit, denoted as an online checker, introduces fault tolerance aspects to the unit. The checker is constructed from a model inferred by active automata learning, which is based on communication with a simulator. To implement the learning environment, LearnLib library has been employed. It provides active automata learning algorithms and their optimizations. An experimental platform enabling controlled fault injection into a design in FPGA was designed and implemented. The platform was used to test the capabilities of the obtained checker. The experimental results show that the error rate is reduced by more than 98% if the checker and reconfiguration is used.
Úplný záznam

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