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Analysis and design of decoupling capacitors in the 65 nm CMOS digital standard library
Kučera, Radek ; Bartoš, Pavel (oponent) ; Král, Vojtěch (vedoucí práce)
This work deals with the design of decoupling capacitors in the form of CMOS transistors for stabilizing the supply voltage in a digital standard library, focusing on 65 nm technology. The introduction provides an overview of CMOS technology and a description of MOS structures. The analysis compares four topologies of decoupling capacitors (NMOS, PMOS, CMOS, Cross-Coupled) and identifies Cross-Coupled as the best choice. The last part focuses on the design and optimization of the layout of decoupling capacitors. Four different layouts were created, optimized for capacity, quality factor, leakage current, and a compromise between these factors, to be integrated into standard digital libraries according to specific applications.
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