Národní úložiště šedé literatury Nalezeno 2 záznamů.  Hledání trvalo 0.00 vteřin. 
Graphical Simulator of Superscalar Processors
Vávra, Jan ; Mrázek, Vojtěch (oponent) ; Jaroš, Jiří (vedoucí práce)
The focus of this thesis is implementation of the superscalar simulator. The implementation follows research of existing simulators and tries to implement missing features from them. Simulator uses RISC-V instruction set architecture, but architecture can be swapped for any RISC instruction set. Simulator implements deterministic branch prediction. Parts of the simulation can be configured. The simulator application also contains a text editor for inputting source code.
Graphical Simulator of Superscalar Processors
Vávra, Jan ; Mrázek, Vojtěch (oponent) ; Jaroš, Jiří (vedoucí práce)
The focus of this thesis is implementation of the superscalar simulator. The implementation follows research of existing simulators and tries to implement missing features from them. Simulator uses RISC-V instruction set architecture, but architecture can be swapped for any RISC instruction set. Simulator implements deterministic branch prediction. Parts of the simulation can be configured. The simulator application also contains a text editor for inputting source code.

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