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Design Retiming na HDL úrovni
Kafka, Leoš ; Matoušek, Rudolf
Článek se zabývá zlepšením časování obvodu pomocí úprav na vyšší úrovni popisu obvodu. Některé nástroje pro syntézu umožňují zlepšení časování, ale tyto techniky nejsou dostupné pro všechny architektury, například pro Atmel FPSLIC. Modifikace na úrovni HDL je nezávislá na použité architektuře a je tak jednou z možností, jak provést zlepšení časování i pro tyto architektury.
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Dynamic reconfiguration of FPGAs: a case study
Matoušek, Rudolf
This paper discusses dynamic reconfiguration achievable using current FPGA methodology. An analysis of implementation issues has been presented and desirable features of future generation of CAD tools have been discussed. Several practical examples have been presented together with their implementation data.
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Dynamic reconfiguration of FPGAs
Matoušek, Rudolf ; Pohl, Zdeněk ; Daněk, Martin ; Kadlec, Jiří
Dymnamic reconfiguration of FPGA devices has been an issue of the last decade. Althouth this new feature of currently available devices permits more robust and flexible designs, it has not been recognized by professionals. This paper disscussed demands placed by dynamic reconfiguration on design tools as well as on designes themselves. A case study is presented for the Atmel AT94K family and the supplied design tools, and values are provided that should aid in analyzing such designs.
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Dynamic runtime partial reconfiguration in FPGA
Matoušek, Rudolf ; Daněk, Martin ; Pohl, Zdeněk ; Kadlec, Jiří
Runtime dynamic reconfiguration of FPGA devices has been an issue of the last decade. Although this feature permits more robust and more flexible designes and devices that posseses it are available on the market, it is not directly supported by the current design tools. This paper presents a simple design that uses true dymnamic reconfiguration for Atmel AT94K devices. The design has been implemented using a special feature of the currently available Figaro IDS5.2 tool in an innovative way.
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Extension for Xilinx System Generator - logarithmic arithmetic blockset
Líčko, Miroslav ; Métais, B. ; Tichý, Milan ; Matoušek, Rudolf
The paper introduces support of floating point(FP) data format for the Xilinx System Generator (XSG) using logarithmic arithmetic. This type of arithmetic seems to be one of the promising ways to solve FP sort of DSP problems in practice. Our 32-bit high-speed logarithmic arithmetic (HSLA) keeps the accuracy according to IEEE 754 and speed up some kinds of FP algorithms. Promising is 19-bit equivalent utilised int this paper. It offers reasonable precision for the practical use and has min.HW requirements.
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