|
|
FPGA implementation of artificial neural network
Čermák, Justin ; Šteffan, Pavel (referee) ; Bohrn, Marek (advisor)
This master's thesis describes the design of effective working artificial neural network in FPGA Virtex-5 series with the maximum use of the possibility of parallelization. The theoretical part contains basic information on artificial neural networks, FPGA and VHDL. The practical part describes the used format of the variables, creating non-linear function, the principle of calculation the single layers, or the possibility of parameter settings generated artificial neural networks.
|
|
|
Implementation of ethernet communication inteface into FPGA chip
Skibik, Petr ; Fujcik, Lukáš (referee) ; Bohrn, Marek (advisor)
The thesis deals with the implementation of Ethernet-based network communication interface into FPGA chip. VHDL programming language is used for description of the hardware. The interface includes the implementation of link-layer Ethernet protocol and network protocols such as IPv4, ARP, ICMP and UDP. The final design allows bi-directional communication on the transport-layer level of TCP/IP model. The designed interface was implemented into Virtex5 FPGA chip on development board ML506 by Xilinx.
|
|
|
Microprocessor system IP core generator
Kerber, Rostislav ; Tošovský, Petr (referee) ; Kubíček, Michal (advisor)
This master’s thesis deal’s with VHDL programming language, ISE Webpack design system and PicoBlaze microprocessor. The thesis describes essentials of VHDL programming language and its application. A simple introduction to ISE Webpack design environment is given. The thesis describes common peripherals and the PicoBlaze processor is described too, including its parameters and implementation aspects. Finally the thesis describes IP generator for generating complex FPGA design including Picoblaze processor.
|
|
|
FPGA based sound card for PC
Štraus, Pavel ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
This project deals with implementation of a first order Sigma–Delta AD converter on the FPGA. This ADC is design for an audio signal processing. ADC is build up partially from digital blocks implemented in FPGA (programmed using VHDL) and from few analog components placed external to FPGA. Output from ADC is PCM signal. Data from ADC is created UDP datagram, which is sent to PC via network connection. Income data are received in created program, which save data to text file. This text file is processing in MATLAB.
|
|
|
Construction of The GPS Devices
Hort, Marek ; Jaroš, David (referee) ; Šteffan, Pavel (advisor)
Aim of this Diploma thesis was to create a device capable of receiving navigational data from GPS. These data are subsequently stored in fixed memory and after connection with the PC are displayed it on the satellite map. The device was realized by using FPGA and GPS module LEA-5s. Description was created in the VHDL language, which was implemented into the circuit. The part of VHDL design was description of PICOBLAZE processor that controls whole system. For displaying and archiving data stored in device was created PC application GPS TRACER. It is able to display stored trace on the satellite map by using Google maps server. For created device were designed and manufactured PCBs, which were manually fitted.
|
|
|
Dynamic reconfiguration with Atmel FPSLIC
Jančík, Martin ; Hanák, Pavel (referee) ; Fedra, Zbyněk (advisor)
This study describes the platform Atmel FPSLIC, which is created by means of the logic arrays FPGA and the micro-sequencer controller AVR. The developmental kit STK594 is described here as well, with its programming possibilities, as for the logic arrays FPGA, as for the micro-sequencers AVR. Also the separate circuit AT94K is described there. This circuit can be programmed by the language VHDL (the field FPGA), or by means of the assembler and language C for the micro-sequencer. All this can be integrated into the one output file by means of program System Designer, comprising a set of software tools for given programming languages and for generation of the whole circuit. Furthermore, the study describes a simple application for the both platform parts. Also the description of the dynamic reconfiguration of the circuit gate part is included.
|
|
|
OFDM demodulator implementation in FPGA
Solar, Pavel ; Urban, Josef (referee) ; Maršálek, Roman (advisor)
The master's thesis briefly analyses the principle of OFDM modulation, possibilities of the synchronization and channel estimation in OFDM. The simply model of OFDM system is made in MATLAB. Because of the implementation in FPGA is generated the behavioral description of the OFDM demodulator through the combination of the schematics description and the description in the VHDL language. The ISE development environment is used.
|
|
|
Design of hardware cipher module
Bayer, Tomáš ; Stančík, Peter (referee) ; Sobotka, Jiří (advisor)
This diploma’s thesis discourses the cryptographic systems and ciphers, whose function, usage and practical implementation are analysed. In the first chapter basic cryptographic terms, symmetric and asymetric cryptographic algorithms and are mentioned. Also usage and reliability are analysed. Following chapters mention substitution, transposition, block and stream ciphers, which are elementary for most cryptographic algorithms. There are also mentioned the modes, which the ciphers work in. In the fourth chapter are described the principles of some chosen cryptographic algorithms. The objective is to make clear the essence of the algorithms’ behavior. When describing some more difficult algorithms the block scheme is added. At the end of each algorithm’s description the example of practical usage is written. The chapter no. five discusses the hardware implementation. Hardware and software implementation is compared from the practical point of view. Several design instruments are described and different hardware design programming languages with their progress, advantages and disadvantages are mentioned. Chapter six discourses the hardware implementation design of chosen ciphers. Concretely the design of stream cipher with pseudo-random sequence generator is designed in VHDL and also in Matlab. As the second design was chosen the block cipher GOST, which was designed in VHDL too. Both designs were tested and verified and then the results were summarized.
|
|
|
USB communication protocol analysis
Zošiak, Dušan ; Fujcik, Lukáš (referee) ; Šteffan, Pavel (advisor)
Tato práce je zaměřena na zpracování a analýzu USB komunikačního protokolu a implementace jeho jednotlivých částí do FPGA obvodu s využitím programovacího jazyka VHDL. Ve finální podobě by měla práce představovat souhrnný a ucelený dokument popisující principy USB rozhraní a jeho komunikace doplněných praktickým návrhem v jazyce VHDL, který by byl schopen převést data do USB.
|
|
|
Methods for quadrature modulator imbalance compensation
Povalač, Karel ; Valenta, Václav (referee) ; Maršálek, Roman (advisor)
Quadrature modulator (demodulator) is used in transmitting (receiving) part of many devices. Unwanted imbalance can influence amplitude, phase or DC offset of modulator (demodulator). Correction of imbalance was a main subject of thesis. Simulations of these methods were created in MATLAB and results were compared. Basics of methods were implement on programmable logic field by program Xilinx ISE. Development kit V2MB1000 with analogue board Memec P160 was chosen for this purpose. In the last part were compare simulation results with practical measurement.
|
guest ::
