Národní úložiště šedé literatury Nalezeno 14 záznamů.  1 - 10další  přejít na záznam: Hledání trvalo 0.00 vteřin. 
Extension for Xilinx System Generator - logarithmic arithmetic blockset
Líčko, Miroslav ; Métais, B. ; Tichý, Milan ; Matoušek, Rudolf
The paper introduces support of floating point(FP) data format for the Xilinx System Generator (XSG) using logarithmic arithmetic. This type of arithmetic seems to be one of the promising ways to solve FP sort of DSP problems in practice. Our 32-bit high-speed logarithmic arithmetic (HSLA) keeps the accuracy according to IEEE 754 and speed up some kinds of FP algorithms. Promising is 19-bit equivalent utilised int this paper. It offers reasonable precision for the practical use and has min.HW requirements.
Floating-Point-Like Arithmetic for FPGA
Matoušek, Rudolf ; Líčko, Miroslav ; Heřmánek, Antonín ; Softley, C.
In recent years we have investigated the use of a logarithmic number representation as an alternative to floating-point. Efficient techniques have been developed to facilitate arithmetic comparable to single precision floating-point in the logarithmic domain.
Prototyping of DSP algorithms on FPGA
Líčko, Miroslav ; Tichý, Milan ; Heřmánek, Antonín ; Matoušek, Rudolf ; Pohl, Zdeněk
Poster describes an algorithm development process for FPGA. The process is shown on the example of an implementation of the QR RLS algorithm.
Utilization of Matlab for the logarithmic processor development
Líčko, Miroslav ; Matoušek, Rudolf ; Pohl, Zdeněk
Microprocessors are using the floating-point units for the real data type manipulation. Basic research has indicated, that the logaritmic number system can offer new possibilities of implementation for the algorithms, especially for algorithms widely using multiplication, division and square root operations. In this article there's a short summary of the development, evavaluation and demonstration with the utilization of Matlab.
Tuning and implementation of DSP algorithms on FPGA
Líčko, Miroslav ; Pohl, Zdeněk ; Matoušek, Rudolf ; Heřmánek, Antonín
The article describes an algoritms development process for FPGA. It is shown on the example of the implementation of the QR RLS algorithm. To realise it means to perform operations such multiplication, division and square root.The research indicates, that the logarithmic arithemtic unit can reused for the real data type processing in some cases such a QR RLS algoritm.The developed prototype of logaritmic unit is tested on DSP algorithms using Matlab.

Národní úložiště šedé literatury : Nalezeno 14 záznamů.   1 - 10další  přejít na záznam:
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1 Ličko, M.
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