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	Floating-Point-Like Arithmetic for FPGA Matoušek, Rudolf ; Líčko, Miroslav ; Heřmánek, Antonín ; Softley, C. In recent years we have investigated the use of a logarithmic number representation as an alternative to floating-point. Efficient techniques have been developed to facilitate arithmetic comparable to single precision floating-point in the logarithmic domain. Detailed record
	RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic Kadlec, Jiří ; Albu, F. ; Softley, Ch. ; Matoušek, Rudolf ; Heřmánek, Antonín Detailed record
	32-bit Logarithmic ALU for Handel-C 2.1 and Celoxica DK1 Kadlec, Jiří ; Heřmánek, Antonín ; Softley, Ch. ; Matoušek, Rudolf ; Líčko, Miroslav Detailed record
	Pipelined Logarithmic 32bit ALU for Celoxica DK1 Heřmánek, Antonín ; Kadlec, Jiří ; Matoušek, Rudolf ; Líčko, Miroslav ; Softley, Ch. Detailed record
	Floating-Point-Like Arithmetic for FPGA Matoušek, Rudolf ; Líčko, Miroslav ; Heřmánek, Antonín ; Softley, Ch. Detailed record
	Implementation of Normalized RLS Lattice on Virtex Albu, F. ; Kadlec, Jiří ; Softley, Ch. ; Matoušek, Rudolf ; Heřmánek, Antonín Detailed record
	Arithmetic on the European Logarithmic Microprocessor Coleman, J. N. ; Chester, E. I. ; Softley, Ch. ; Kadlec, Jiří Detailed record

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