|
|
Implementation of system for IC testing via JTAG interface
Prášil, Pavel ; Zachariášová, Marcela (referee) ; Petyovský, Petr (advisor)
This master thesis deals with testing integrated circuits containing RISC-V processor core using JTAG protocol. This thesis objective is to design a module for 2-wire JTAG protocol support and design of an extending protocol for RISC-V processor system bus access. Designed module will be used for the integrated circuit testing using a 2-wire JTAG interface in order to reduce the number of pins dedicated for JTAG interface. The extending protocol will be used to reduce time spent by integrated circuits testing. The thesis contains description of the RISC-V testing system, design and implementation of module for 2-wire JTAG protocol support and also design and implementation of module for system bus access by the extending protocol. The thesis also includes extension of testing SW environment by support of communication using the extending protocol and verification of HW solution functionality. The thesis contain evaluation of time efficiency of implemented communication solution.
|
|
|
Modernization of educational exercises of the course Logical circuits and systems
Prášil, Pavel ; Holek, Radovan (referee) ; Petyovský, Petr (advisor)
This bachelor thesis deals with the design of an asynchronous serial receiver/transmitter and its implementation into the FPGA. The design will be used as a laboratory exercise in the course "Logical circuit and systems". This paper contains a description of the features of serial communication interface UART. The thesis includes the final design of an asynchronous serial receiver/transmitter and the simulation outputs of particular parts. The final design of UART will be used as a communication interface for music playback by the programmable multichannel sound generator. Design of the programmable multichannel sound generator is not a part of this thesis, but it has been taken from another bachelor thesis.
|
|
|
Universal asynchronous receiver/transmitter implementation in VHDL
Prášil, Pavel ; Petyovský, Petr
The article deals with the design of an asynchronous serial receiver/transmitter and its implementation into the FPGA. The design will be used as a laboratory exercise in the course ”Logical circuits and systems”. This paper contains the basic design of UART and the following features which will be added. UART design will be used as a communication interface between PC and an existing programmable multichannel sound generator (PSG) design, which is already implemented in FPGA.
|
|
|
Modernization of educational exercises of the course Logical circuits and systems
Prášil, Pavel ; Holek, Radovan (referee) ; Petyovský, Petr (advisor)
This bachelor thesis deals with the design of an asynchronous serial receiver/transmitter and its implementation into the FPGA. The design will be used as a laboratory exercise in the course "Logical circuit and systems". This paper contains a description of the features of serial communication interface UART. The thesis includes the final design of an asynchronous serial receiver/transmitter and the simulation outputs of particular parts. The final design of UART will be used as a communication interface for music playback by the programmable multichannel sound generator. Design of the programmable multichannel sound generator is not a part of this thesis, but it has been taken from another bachelor thesis.
|
guest ::
RSS feed.