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Packet Classification Algorithms
Machala, Jiří ; Puš, Viktor (referee) ; Kajan, Michal (advisor)
The main aim of this work is interpretation and implementation of HyperCuts algorithm. It also covers the problematic of packet classification in general - it sums up the basic classification theory and introduces well-known classification methods. It concentrates mostly on evaluation of HyperCuts in comparison to HiCuts algorithm and analyses the assets of optimizations described in professional literature. It proposes a new way to limit the number of memory accesses by combining HyperCuts and HiCuts for single classifier.
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Graphical Demonstration of Selected Route Lookup Algorithm
Ohrádka, Marek ; Kaštil, Jan (referee) ; Puš, Viktor (advisor)
This bachelor's thesis deals with IP routing and different routing protocols. It describes different solutions of the longest prefix matching, advantages and disadvantages of different approaches. Shows the concept of the trie data structure and its alternatives. Describes the Shape Shifting Trie data structure in detail, as well as process of its creation and the way of traversing the nodes in SST route lookup algorithm. At last, application design and implementation is described. Main purpose of the application is to graphically demonstrate the function of SST route lookup algorithm. This thesis shows decomposition approach to this task, describes major problems and its solution.
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SystemVerilog Verification of FrameLink Protocol Tools
Santa, Marek ; Martínek, Tomáš (referee) ; Puš, Viktor (advisor)
In the development process of digital circuits, it is often not possible to avoid introducing errors into systems that are being developed. Early detection of such errors saves money and time. This thesis deals with functional verification of various data processing components. General functional verification principles and practices are discussed and design and implementation of a SystemVerilog verification environment is described in detail. The verification results are summarized and evaluated.
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Graphical Demonstration of Selected Route Lookup Algorithm
Olejník, Tomáš ; Kaštil, Jan (referee) ; Puš, Viktor (advisor)
This thesis briefly describes principe of networks, routing protocols and there are described basis of some existing longest prefix match algorithms, which are implemented in router's hardware. Main part of thesis deals with a Tree Bitmap algorithm, that demonstration program creating is an objective of this work. The principe of this algorithm is demonstrated by visual animations.
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Verification of FPGA Generic Interconnection System
Bartoš, Václav ; Martínek, Tomáš (referee) ; Puš, Viktor (advisor)
This thesis deals with design, implementation and realization of simulation verification of generic interconnection system for FPGA chips. This system is part of the NetCOPE platform developed in the Liberouter project, within which was this work done. In the beginning, an usual methods of verification in SystemVerilog language are described. Then there is a brief description of the interconnection system, aimed especially to aspects important to verification. The main part of the thesis is design of verification environment and control program of test for all three components of the tested system. It started form the earlier described principles, that are established in the Liberouter project, and it add some more features. All components of the verification environment are designed to be general and reusable, so they can be used also in other verifications related to the interconnection system. At the end of the thesis, there are discussed results of the verification, found bugs and the general advantages of simulation verifications.
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Library for Operations over Finite Automata
Bartůněk, Petr ; Puš, Viktor (referee) ; Kaštil, Jan (advisor)
This work deals with two basic operations over finite automata. Determination of nondeterministic finite automata and minimization of deterministic finite automata. For these two operations I proposed sequential algorithms that are parallelizable. I deal mainly with finding the speedup of SSE instructions, or use the OpenMP library. The trend today is mainly in increasing the number of processors, so I propose parallel algorithms for multiple processors. When searching for the optimal solution, I will be to examine other ways to achieve speedup, for example efficient saving of the data structures in memory.
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Implementation of Image Classifiers in FPGAs
Kadlček, Filip ; Puš, Viktor (referee) ; Fučík, Otto (advisor)
The thesis deals with image classifiers and their implementation using FPGA technology. There are discussed weak and strong classifiers in the work. As an example of strong classifiers, the AdaBoost algorithm is described. In the case of weak classifiers, basic types of feature classifiers are shown, including Haar and Gabor wavelets. The rest of work is primarily focused on LBP, LRP and LR classifiers, which are well suitable for efficient implementation in FPGAs. With these classifiers is designed pseudo-parallel architecture. Process of classifications is divided on software and hardware parts. The thesis deals with hardware part of classifications. The designed classifier is very fast and produces results of classification every clock cycle.
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Longest Prefix Match Algorithms
Weigner, Martin ; Puš, Viktor (referee) ; Tobola, Jiří (advisor)
The speed of computer network is increasing. One of the basic tasks which has to be solved by the network devices is longest prefix match. Many algorithms are able to solve this task but it's necessary to solve it very fast because of increasing transfer speed and the routing standard IPv6. This standard has longer addresses and it's necessary to search prefixes in much bigger sets. The thesis describes present algorithms that solve the problem. These are confronted with new algorithm HashTreeBitmap which is also described in the work. On the tests is documented that this algorithm is able to cope with high demands which are placed on it.
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