|
|
Design of erosion and flood control measures in the study case area responding to climate change
Mrázek, Vojtěch ; Larišová,, Lucie (referee) ; Sobotková, Veronika (advisor)
The aim of the work is to design anti-erosion and flood protection in the area of interest KÚ Lukavec to the current state and responding to climate change. At the same time, it is necessary to assess the degree of erosion threat to the soil and analyze runoff conditions in critical areas. The introductory part summarizes information about the studied area and methods for calculation. The erosion analysis is processed in the design part and suitable anti-erosion and anti-flood measures will be proposed. DesQ-MaxQ software was used to calculate the runoff conditions, graphical outputs and analysis of erosion conditions were created in the ArcGIS environment.
|
|
|
Movement Abnormalities Classification using Genetic Programming
Chudárek, Aleš ; Mrázek, Vojtěch (referee) ; Drahošová, Michaela (advisor)
When suppressing the symptoms of Parkinson's disease, the correct dosage of drugs is critical for the patient. Improper dosing can either cause insufficient suppression of symptoms or, conversely, side effects, such as dyskinesia, occur with high doses. Dyskinesia is manifested by involuntary muscle movement. This work deals with the automated classification of dyskinesia from motion data recorded using a triaxial accelerometer located on the patient's body. In this work, the classifier of dyskinesia is automatically designed using Cartesian genetic programming. The designed classifier achieves very good quality of classification of severe dyskinesia (AUC = 0,94), which is a comparable result to the techniques presented in scientific literature.
|
|
|
Acceleration of Symbolic Regression Using Cartesian Genetic Programming
Hodaň, David ; Mrázek, Vojtěch (referee) ; Vašíček, Zdeněk (advisor)
This thesis is focused on finding procedures that would accelerate symbolic regressions in Cartesian Genetic Programming. It describes Cartesian Genetic Programming and its use in the task of symbolic regression. It deals with the SIMD architecture and the SSE and AVX instruction set. Several optimizations that lead to a significant acceleration of evolution in Cartesian Genetic Programming are presented. A method of a bit-level parallel simulation that uses AVX2 vectors allows to process 256 input combinations of a logic circuit in paralell. Similarly it is possible to use a byte-level parallel simulation and work with 32 bytes when evolving an image filter. A new method of batch mutation can accelerate the evolution of combinational logic circuits thousand times depending on the problem size. For example, using a combination of these and other methods the evolution of 5 x 5b multipliers took 5.8 seconds on average on an Intel Core i5-4590 processor.
|
|
|
A Generator of Arithmetic Circuits
Klhůfek, Jan ; Vašíček, Zdeněk (referee) ; Mrázek, Vojtěch (advisor)
The aim of this bachelor thesis is to present the design and implementation of an arithmetic circuit generator. The generator focuses on generating various output representations of arithmetic circuits in flattened and hierarchical forms using the Python programming language. The work first deals with the specification of HW structures of individual arithmetic circuits and the corresponding ways of describing these structures into various representations. Followed by an introduction to the concept and details of the implementation of a tool called ArithsGen, which is able to generate arithmetic circuits and export them to various output representations. The output representations are then used for fast and simple simulation of the designed circuits (C), to describe the hardware structures and perform logic synthesis (Verilog), to formal verify the designs (BLIF) or to globally optimize the circuits using the evolutionary strategy (CGP). Finally, the generated representations were individually tested and compared with each other using the results obtained from logic synthesis.
|
|
|
Intelligent Access Control System for Large Facilities
Truhlář, Jan ; Mrázek, Vojtěch (referee) ; Vašíček, Zdeněk (advisor)
Aim of this work is to create autonomous embedded device which allows access control with radio frequency identification (RFID). Device is configurable by web interface and offers access history. Updates of RFID cards database are realised by mesh network. For realisation of this work is used developement kit based on Espressif Systems ESP8266 chip, which is programmed with open-source platform Arduino. Created device can be used in locations without direct network covrage.
|
|
|
Approximation of Digital Circuits in Yosys Tool
Plevač, Lukáš ; Vašíček, Zdeněk (referee) ; Mrázek, Vojtěch (advisor)
The goal of this work is introduction of cgploss extension. This extension is extension for combinational logic circuits optimization in Yosys tool. Cartesian genetic programming is introduced in the first part of this work. Cartesian genetic programming is a design and optimization method that can be used for circuit optimization and approximation. This chapter introduces representation of combinational logic circuits for Cartesian genetic programming. The next chapter introduces Yosys tool and possibilities of the Yosys extending. The proposed 'cgploss' extension is introduced in the next chapter. The chapter also provides details about the implementation and the usage. The last chapter tests cgploss extension and compares representation of combinational logic circuits.
|
|
|
Library for Visualization of Digital Circuits
Scherfel, Walter ; Mrázek, Vojtěch (referee) ; Vašíček, Zdeněk (advisor)
This bachelor thesis is devoted to the automated schematic generation. The primary goal is to design and implement a library for visualization of digital circuits. The library is implemented in C++ language and depends on a popular Boost (used for work with XML structure and parsing input) and Qt (used for visualization) library. The library is designed in such a way that it can be easily embedded into a user application.
|
|
|
Acceleration of Transistor-Level Evolutionary Design of Digital Circuits Using Zynq
Mrázek, Vojtěch ; Sekanina, Lukáš (referee) ; Vašíček, Zdeněk (advisor)
The goal of this project is to design a hardware unit that is designed to accelerate evolutionary design of digital circuits on transistor level. The project is divided to two parts. The first one describes design methods of the MOSFET circuits and issues of evolutionary algorithms. It also analyses current results in this domain and provides a new method for the design and optimization. The second part describes proposed unit that accelerates the new method on the circuit Zynq which integrates ARM processor and programmable logic. The new method functionality has been empirically analysed in the task of optimization of few circuits with more inputs. The hardware unit has been tested for designing of gates on transistor level.
|
|
| |
|
|
Application of SAT Solvers in Circuit Optimization Problem
Minařík, Vojtěch ; Mrázek, Vojtěch (referee) ; Vašíček, Zdeněk (advisor)
This thesis is focused on the task of application of SAT problem and it's modifications in area of evolution logic circuit development. This task is supposed to increase speed of evaluating candidate circuits by fitness function in cases where simulation usage fails. Usage of SAT and #SAT problems make evolution of complex circuits with high input number significantly faster. Implemented solution is based on #SAT problem. Two applications were implemented. They differ by the approach to checking outputs of circuit for wrong values. Time complexity of implemented algorithm depends on logical complexity of circuit, because it uses logical formulas and it's satisfiability to evaluate logic circuits.
|
guest ::
RSS feed.