National Repository of Grey Literature 211 records found  beginprevious192 - 201next  jump to record: Search took 0.00 seconds. 
Industrial HD camera interface
Juřica, Libor ; Dvořák, Vojtěch (referee) ; Bohrn, Marek (advisor)
Master´s thesis deals with creating circuit for receiving data from industrial camera. IP Core is designing for FPGA. Theoretical part of the work describes SDI interface, analysis of relevant SMPTE standards and specification of data format. The thesis include general characteristics of multigigabit transceivers. Practical part include VHDL description of SDI receiver. Thesis presents simulations of created circuit, implementation for real application and measurement results for signal transmission over slip ring.
Implementation of fast serial bus on FPGA
Drbal, Jakub ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources.
Modern methods of mixed-signal integrated circuit verification
Hradil, Jaroslav ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Tato diplomová práce se zabývá verifikací integrovaných obvodů pracujících ve smíšeném módu. Teoretická část práce obsahuje přehled moderních verifikačních metod a zaměřuje se zejména na „assertion based methodology“ . V praktické části práce jsou pak rozebrány popisné jazyky používané u této metody, a následně je vytvořen kód pro verifikaci bloku řídícího obvodu spínaných zdrojů.
FFT implementation in FPGA and ASIC
Dvořák, Vojtěch ; Bohrn, Marek (referee) ; Fujcik, Lukáš (advisor)
The aim of this thesis is to design the implementation of fast Fourier transform algorithm, which can be used in FPGA or ASIC circuits. Implementation will be done in Matlab and then this form of implementation will be used as a reference model for implementation of fast Fourier transform algorithm in VHDL. To verify the correctness ofdesign verification enviroment will be created and verification process wil be done. Program that will generate source code for various parameters of the module performing a fast Fourier transform will be created in the last part of this thesis.
Heat pumps – practical experience
Dvořák, Vlastimil ; Pešek, Martin (referee) ; Jaroš, Michal (advisor)
The main aim of the bachelor‘s work is to collect available data about realized projects of heat pumps and to consider their suitability, convenience and economic return of the investment. Further objective is to consider the economy viewpoint of heat pumps and suitability of their instalations.
Concrete ribbed slab
Dvořák, Vít ; Perla, Jan (referee) ; Strnad, Jiří (advisor)
The bachelor thesis deals with a design of monolithic reinforced concrete, line supported and cross reinforced slab and a design of supporting reinforced concrete ribs. The plan of the slabs is rectangular and one time bent. The content bachelor thesis is calculation and design of reinforcement of slab and ribs. For the calculation was used software Scia Engineer 14 and was checked by manually calculation. The slab is located in the first floor of polyfunctional house. Other parts of the object are not covered by the thesis.
Fenologie lesních dřevin ve smíšeném porostu na polesí Bílovice nad Svitavou
Dvořák, Vojtěch
The phenological research was inquired into the Sessile Oak (Querus petraea Matt. Liebl.) and European Larch (Larix decidua Mill.) on the explorative area of ŠLP ML Křtiny which belongs to the forest district of Bílovice nad Svitavou. These two trees were in the 35 years old mixed stand. On the monitored trees, there were compared the beginnings and the durations of the particular phenological stages in the connection with the weather conditions in the particular year. The temperature fluctuations for the phenological stages were specified by sum of effective air temperatures higher than 5 °C and 0 °C. There were compared the duration of the spring and autumn phenological stages on the Sessile Oak and European Larch. The gained results were compared with the statements of other authors in the Czech Republic and abroad. There were also done the comparison of the beginnings and durations of particular phenological stages of the trees with the datas of the long--standing observation ČHMÚ on the area of the same height above sea level in the Czech Republic.
Využití procesního modelování pro inovace procesů ve firmě Morfico s.r.o.
Dvořák, Viktor
This thesis deals with analysis of real processes in company Morfico s.r.o., which does business in the market of construction materials. The processes are modeled using UML 2.0 and BPMN 2.0 notation using CASE tool Enterprise Architect. Thereafter is per-formed their analysis and evaluation of their effectiveness. Based on the analysis of in-novation processes are executed and one of the innovations is implemented as a web application using PHP and MySQL technologies.

National Repository of Grey Literature : 211 records found   beginprevious192 - 201next  jump to record:
See also: similar author names
7 DVOŘÁK, Vlastimil
19 DVOŘÁK, Vojtěch
19 DVOŘÁK, Václav
19 DVOŘÁK, Vít
2 Dvořák, Viktor
2 Dvořák, Vilém
2 Dvořák, Vladimír
3 Dvořák, Vladimír,
1 Dvořák, Vladislav
7 Dvořák, Vlastimil
19 Dvořák, Vojtěch
1 Dvořák, Vojtěch Adalbert
19 Dvořák, Václav
19 Dvořák, Vít
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