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National Repository of Grey Literature

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	32-bit Logarithmic ALU for Handel-C 2.1 and Celoxica DK1 Kadlec, Jiří ; Heřmánek, Antonín ; Softley, Ch. ; Matoušek, Rudolf ; Líčko, Miroslav Detailed record
	Pipelined Logarithmic 32bit ALU for Celoxica DK1 Heřmánek, Antonín ; Kadlec, Jiří ; Matoušek, Rudolf ; Líčko, Miroslav ; Softley, Ch. Detailed record
	The European Logarithmic Microprocessor - a QRD RLS Applications Coleman, J. N. ; Kadlec, Jiří ; Matoušek, Rudolf ; Pohl, Zdeněk ; Heřmánek, Antonín Detailed record
	A Comparison of FPGA Implementation of the A Priori Error-Feedback LSL Algorithm using Logarithmic Arithmetic Albu, F. ; Kadlec, Jiří ; Matoušek, Rudolf ; Heřmánek, Antonín ; Coleman, J. N. Detailed record
	Floating-Point-Like Arithmetic for FPGA Matoušek, Rudolf ; Líčko, Miroslav ; Heřmánek, Antonín ; Softley, Ch. Detailed record
	Implementation of Normalized RLS Lattice on Virtex Albu, F. ; Kadlec, Jiří ; Softley, Ch. ; Matoušek, Rudolf ; Heřmánek, Antonín Detailed record
	Tuning and implementation of DSP algorithms on FPGA Líčko, Miroslav ; Pohl, Zdeněk ; Matoušek, Rudolf ; Heřmánek, Antonín The article describes an algoritms development process for FPGA. It is shown on the example of the implementation of the QR RLS algorithm. To realise it means to perform operations such multiplication, division and square root.The research indicates, that the logarithmic arithemtic unit can reused for the real data type processing in some cases such a QR RLS algoritm.The developed prototype of logaritmic unit is tested on DSP algorithms using Matlab. Detailed record
	Pipelined logarithmic 32bit ALU for Celoxica DK1 Heřmánek, Antonín ; Kadlec, Jiří ; Matoušek, Rudolf ; Líčko, Miroslav ; Pohl, Zdeněk This paper presents and compares two possible solution for floating point-like HW, based on a 32bit logarithmic ALU. There are described the implementation, parametres nad the basic use of a non-pipelined ALU. Both Virtex FPGA cores are encapsulated in function like API interface compatible with Handel-C 2.1 and the new DK1 tool from Celoxica. Detailed record
	Alpha accelerator for RTW - Windows Target Líčko, Miroslav ; Matoušek, Rudolf ; Heřmánek, Antonín Detailed record
	FPGA implementation of logarithmic unit Heřmánek, Antonín ; Matoušek, Rudolf ; Líčko, Miroslav ; Kadlec, Jiří Detailed record

National Repository of Grey Literature : 24 records found   11 - 20  jump to record:

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2	HEŘMÁNEK, Aleš

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