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Asynchronous communication interfaces in FPGA
 Cabal, Jakub ; Fujcik, Lukáš (referee) ; Bohrn, Marek (advisor)
The aim of this thesis is to analyze the options for implementation of asynchronous modules for clock domain crossing in an FPGA circuit. Such crossings are inevitable in moderately complex firmware designs and can lead to data corruption or loss, if implemented incorrectly. Furthermore, the work deals with application of correct constraints. The practical part of this work describes an implemented library of clock domain crossing modules. Further, the practical part describes a created methodology for use of clock domain crossing modules, whose application is demonstrated in a case study of a network interface card circuit created for the acceleration card COMBO-80G.
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