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Application for managing FPGA cards
Ostrý, Pavel ; Ilgner, Petr (referee) ; Dobiáš, Patrik (advisor)
This bachelor's thesis focuses on the management of FPGA (Field Programmable Gate Array) cards within the context of the VUT FEKT school system. FPGA cards are devices that enable hardware programming using programmable logic circuits, which significantly enhances the efficiency of specific tasks that requires low latency and high data throughput. Despite the growing popularity of FPGA cards, there is no graphical applications, that would enable their management in school system enviroment. The aim of this thesis is to develop an application that enables configuration, monitoring, and control of FPGA cards through a graphical user interface. The thesis is divided into ten chapters, with the first five covering the theoretical part and the remaining five focusing on practical implementation. The theoretical part includes an introduction to FPGA cards, their comparison with other similar devices, a description of their programming, and an analysis of the requirements for the final application, followed by the selection of suitable tools. The practical part concentrates on the implementation of the user interface, code structure, and the description of individual program classes and functions. The result of the work is a graphical application that meets all specified requirements and enables configuration, monitoring, and control of FPGA cards within the VUT FEKT environment. The application was developed in the Java programming language, with the graphical interface implemented using JavaFX. Communication with the FPGA card is handled using the libnfb library, which is written in C, with its functions mapped through JNA. This bachelor's thesis delivers an FPGA card management application developed based on the needs of VUT FEKT.
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Remote laboratory for PYNQ
Veselý, Boris ; Šimek, Václav (referee) ; Mrázek, Vojtěch (advisor)
This thesis is used to provide PYNQ devices to multiple users for teaching the IVH subject. The remote laboratory application provides access to the PYNQ devices using tunnel connections. The application can manage the files stored on the server and register the time slots during which the user will be allowed to access the PYNQ devices using tunnel connections. The application also allows an administrator role that can manage users, their reservations and individual PYNQ devices. The application is written using PHP, the Nette framework and Go. The contribution of the work is to simplify access to PYNQ devices in the context of teaching the IVH subject.
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Design and implementation of display sniffer on embedded targets
Lipták, Samuel ; Šnajder, Jan (referee) ; Krejsa, Jiří (advisor)
Táto diplomová práca sa zaoberá overením funkcionality grafického rozhrania v integrovaných systémoch. Súčasné prístupy využívajúce kamerové systémy pre optickú kontrolu sú charakterizované nedostatočnou spoľahlivosťou, vysokými nákladmi, náročnou údržbou a náročnosťou na priestorové umiestnenie. Cieľom tejto práce je analyzovať a navrhnúť nový prístup k získavaniu grafických dát, ktorý bude založený na spoľahlivej technológii. Konkrétne riešenie využíva technológiu FPGA (Field-Programmable Gate Array) a celý systém je implementovaný na vývojovej platforme PYNQ. Táto platforma zároveň obsahuje server s API, čo umožňuje jednoduchší prístup k získaným dátam. Výsledkom tejto práce je nová metóda overenia funkcionality grafického rozhrania vstavaných systémov, ktorá bude spĺňať požadované kritériá spoľahlivosti a účinnosti. Takýto prístup by mohol nájsť uplatnenie v priemysle a prispieť k zlepšeniu kvality a efektívnosti kontroly kvality integrovaných systémov.
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Cryptographic schemes implementation on small FPGA platforms
Pukšová, Ráchel ; Cíbik, Peter (referee) ; Dobiáš, Patrik (advisor)
The objective of the bachelor thesis is to implement the AES-GCM encryption algorithm on a Nexys A7-100T FPGA board. It introduces the issues of cryptography and authentication in data transmission as well as describes the FPGA technology. The implementation has been done in VHDL, as a hardware description language. It analyses the project provided by the Institute of Telecommunications of Brno University of Technology, which is intended to be modified to achieve the stated goal. In the practical part, it discusses the modifications made and the tests that verified the functionality of the implementation. It compares resource utilization with the original project as a tool to better understand the impact of the modifications made. This work is also compared with existing AES-GCM solutions. Finally, suggestions are given for further modifications that could be made to achieve lower goals.
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RF WiFi network analyzer
Kvasničák, Dušan ; Zamazal, Michal (referee) ; Valach, Soběslav (advisor)
The goal of this thesis is the design and implementation of a WiFi network monitor analyzer in the 2.4 and 5 GHz radio frequency bands using a software radio. The work focuses on obtaining and analyzing data from these bands with the aim of extracting information about the state and movement of devices, their position in relation to the analyzer, and estimating the number of people moving in the monitored space.
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Graphics display unit
Szkandera, Filip ; Dvořák, Vojtěch (referee) ; Dvorský, Adam (advisor)
The goal of this thesis is to learn about the function of a graphical unit and to design a simple version of it. The first chapter consists of a theory about a different connectors and protocols, that were typically used in graphical applications throughout history. Based on this theoretical analysis the best connector and a protocol for a graphical application is chosen. In the practical part of this thesis, the graphical unit is designed firstly using only logic integrated circuits and then using an FPGA.
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Multiaxis feedback cooling of particle in optical trap
Číž, Adam ; Adámek, Roman (referee) ; Brablc, Martin (advisor)
This thesis deals with a design and implementation of algorithms for multiaxis feedback cooling (which means positional control) of a particle in an optical trap with use of Kalman filter. Two control methods are proposed here, each of which is intended for use of a different actuator: a laser intensity modulator or a pair of electrodes. Next, the implementation of both methods on hardware with an FPGA is described. Functioning of both proposed algorithms is proven by a numerical simulation. In addition, the functioning of the control using electrodes is demonstrated by an experiment with an optical trap. The second method is fully prepared for use in an experiment.
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High-speed data transfer
Šimík, Jakub ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This work deals with the design of a device for sending data from a fast ADC converter to a computer via an Ethernet interface using the MicroZed 7020 development board and the Zynq 7000 system on chip that this board is equipped with. This development board and the Zynq 7000 are first presented in the work, followed by a brief description of the selected protocols, and based on a theoretical analysis, the design of the solution architecture is then carried out. The next part of the work then deals with the implementation of the device in programmable logic and software for the processing system according to the design architecture. The conclusion of the work is dedicated to verifying the correct function of individual parts of the device.
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Neural network inference on the ZYNQ
Masár, Filip ; Bidlo, Michal (referee) ; Mrázek, Vojtěch (advisor)
Neural networks are becoming increasingly popular. Inference is now performed not only on high-end GPUs, but also on low-power embedded systems. This bachelor’s thesis explores ways to test fault tolerance on the hardware accelerator of neural networks. It propose the use of FPGAs to increase the performance of fault tolerance experiments. To achieve this goal, an open-source accelerator NVDLA was used and modified to support fault injection. Furthermore, an analysis of the fault tolerance of ResNet-18 is presented to demonstrate the proposed solution.
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Implementation of HDL module for data preprocessing from multichannel ADC
Matoušek, Petr ; Macho, Tomáš (referee) ; Petyovský, Petr (advisor)
Master’s thesis focuses on designing and implementing digital filters inside FPGA to create versatile VHDL components for data pre-processing. The goal was to develop a reusable solution that efficiently filters input data from an ADC using FIR and CIC filters implemented inside FPGA. Externally, the device operates as a slave component, communicating via the SPI bus for integration into complex data processing systems. Theoretical discussions covers ADC converter fundamentals, FPGA architectures, digital filter theory, and hardware selection. Practical implementation describes VHDL design, optimization for performance, and rigorous real-world testing, including simulation, synthesis, and evaluation with real data inputs. This work produces a VHDL component for data pre-processing, suitable for projects that requires efficient data filtering.
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