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Implementation of a Boot Controller for Intel FPGAs
Hak, Tomáš ; Fukač, Tomáš (referee) ; Matoušek, Jiří (advisor)
This thesis touches the topic of using FPGA technology in the field of computer networks, specifically for hardware acceleration of network traffic processing on a network card developed by the CESNET association. FPGA technology is popular mainly due to the possibility to easily reconfigure the chip and fix any errors or update the firmware. The thesis first discusses the design and implementation of a new unit for Intel FPGA, which will be able to communicate with the external configuration flash memory of the chip featured on the card mentioned above. It then goes on to address the design and implementation of a software tool that will allow, via the newly implemented firmware unit, to load new configuration data into the flash memory and force reconfiguration of the FPGA chip using this newly loaded data. Towards the end of the thesis, the functionality of the newly implemented system is tested in practice.
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Interconnection of AURIX microcontroller with NVIDIA Jetson platform
Smrčka, Michal ; Bartík, Ondřej (referee) ; Blaha, Petr (advisor)
Part of this thesis covers the basics of working with NVIDIA Jetson Nano and AURIX Application Kit platforms, namely TC277 TFT and TC224 TFT. It also theoretically analyzes some peripherals of the platforms. These basics are necessary for the following part, which is focused on the implementation of a serial communication interface for data transfer between platforms. The work describes a program implementation of 2 interfaces: SPI and Ethernet MAC. The communication via SPI (or QSPI in the case of AURIX) is supplemented with the use of GPIO pins, in the case of Ethernet the communication is realized at a link layer using Ethernet frames. The connection via SPI is further tested in a specific application when controlling a BLDC motor using TC224 and AURIX eMotor Drive Kit V2.1, where the measured data is sent to the Jetson Nano for real-time processing.
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Implementation of a Boot Controller for Intel FPGAs
Hak, Tomáš ; Fukač, Tomáš (referee) ; Matoušek, Jiří (advisor)
This thesis touches the topic of using FPGA technology in the field of computer networks, specifically for hardware acceleration of network traffic processing on a network card developed by the CESNET association. FPGA technology is popular mainly due to the possibility to easily reconfigure the chip and fix any errors or update the firmware. The thesis first discusses the design and implementation of a new unit for Intel FPGA, which will be able to communicate with the external configuration flash memory of the chip featured on the card mentioned above. It then goes on to address the design and implementation of a software tool that will allow, via the newly implemented firmware unit, to load new configuration data into the flash memory and force reconfiguration of the FPGA chip using this newly loaded data. Towards the end of the thesis, the functionality of the newly implemented system is tested in practice.
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Interconnection of AURIX microcontroller with NVIDIA Jetson platform
Smrčka, Michal ; Bartík, Ondřej (referee) ; Blaha, Petr (advisor)
Part of this thesis covers the basics of working with NVIDIA Jetson Nano and AURIX Application Kit platforms, namely TC277 TFT and TC224 TFT. It also theoretically analyzes some peripherals of the platforms. These basics are necessary for the following part, which is focused on the implementation of a serial communication interface for data transfer between platforms. The work describes a program implementation of 2 interfaces: SPI and Ethernet MAC. The communication via SPI (or QSPI in the case of AURIX) is supplemented with the use of GPIO pins, in the case of Ethernet the communication is realized at a link layer using Ethernet frames. The connection via SPI is further tested in a specific application when controlling a BLDC motor using TC224 and AURIX eMotor Drive Kit V2.1, where the measured data is sent to the Jetson Nano for real-time processing.
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