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SystemC Memory Subsystem
Michl, Kamil ; Vaňák, Tomáš (referee) ; Hruška, Tomáš (advisor)
This thesis deals with the design and implementation of a processor simulation memory subsystem. The memory subsystem is designed using the Transaction Level Modeling approach. The implementation is done in C++ language utilizing the SystemC library. The processor simulation is adopted from the Codasip company simulator. The objective is to create a functional connection between the processor and the memory inside the simulator. This connection supports communication protocols of AHB3-lite, AXI4-lite, CPB, and CPB-lite buses. The new implementation of the aforementioned connection and the memory is integrated into the original simulator. The resulting simulator is tested using unit tests.
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Software Debugging in Codasip Studio Using JTAG Interface Simulated in RTL Simulator
Michl, Kamil ; Husár, Adam (referee) ; Zachariášová, Marcela (advisor)
This thesis is dealing with an option to connect the RTL simulation of a processor with a software debugger. Acording to my design, the communication between these components is handled using the JTAG and the Nexus interface. The simulation is controlled by a selected interface between hardware and software description languages. For the implementation, following components are used: JTAG adapter created by Codasip, RTL simulator Questa Advanced Simulator created by Mentor, a Siemens Business, and VPI interface for communication between Verilog and C++ languages. Concept presented in this thesis can be used on other implementations that depend on different programs and interfaces. The implementation contained in this thesis was tested and is fully functional. Nowadays, it is used by Codasip company and it will probably be updated and enhanced in the future.
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SystemC Memory Subsystem
Michl, Kamil ; Vaňák, Tomáš (referee) ; Hruška, Tomáš (advisor)
This thesis deals with the design and implementation of a processor simulation memory subsystem. The memory subsystem is designed using the Transaction Level Modeling approach. The implementation is done in C++ language utilizing the SystemC library. The processor simulation is adopted from the Codasip company simulator. The objective is to create a functional connection between the processor and the memory inside the simulator. This connection supports communication protocols of AHB3-lite, AXI4-lite, CPB, and CPB-lite buses. The new implementation of the aforementioned connection and the memory is integrated into the original simulator. The resulting simulator is tested using unit tests.
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Software Debugging in Codasip Studio Using JTAG Interface Simulated in RTL Simulator
Michl, Kamil ; Husár, Adam (referee) ; Zachariášová, Marcela (advisor)
This thesis is dealing with an option to connect the RTL simulation of a processor with a software debugger. Acording to my design, the communication between these components is handled using the JTAG and the Nexus interface. The simulation is controlled by a selected interface between hardware and software description languages. For the implementation, following components are used: JTAG adapter created by Codasip, RTL simulator Questa Advanced Simulator created by Mentor, a Siemens Business, and VPI interface for communication between Verilog and C++ languages. Concept presented in this thesis can be used on other implementations that depend on different programs and interfaces. The implementation contained in this thesis was tested and is fully functional. Nowadays, it is used by Codasip company and it will probably be updated and enhanced in the future.
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