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Development of Simulation Models of P4 Language
Bulička, Miroslav ; Matoušek, Jiří (referee) ; Martínek, Tomáš (advisor)
CESNET association is developing tool that allows running P4 programs on field programmable gate array. This tool is used in design of digital circuit, which goes through verification process. The verification uses behavioral model, which does not fully meet requirements. This thesis deals with introduction to P4 language, creation of behavioral models and developing of behavioral model, which meets the requirements of CESNET association. Current behavioral model, used in verification process, will be replaced by developed model. Project Behavioral Model version 2 was used for developing of behavioral model. Behavioral model simple switch was used as default model. This model is edited based on requirements of CESNET association. Result of this thesis is behavioral model which meets the requirements.
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Network Traffic Simulation and Generation
Matoušek, Jiří ; Kořenek, Jan (referee) ; Korček, Pavol (advisor)
Development of computer networks able to operate at the speed of 10 Gb/s imposes new requirements on newly developed network devices and also on a process of their testing. Such devices are tested by replaying synthetic or previously captured network traffic on an input link of the tested device. We must be able to perform both tasks also at full wire speed. Current testing devices are either not able to operate at the speed of 10 Gb/s or they are too expensive. Therefore, the aim of this thesis is to design and implement a hardware accelerated application able to generate and replay network traffic at the speed of 10 Gb/s. The application is accelerated in the FPGA of the COMBOv2 card and it also utilizes the NetCOPE platform. Architecture of the application is modular, which allows easy implementation of different modes of operation. The application implements both capturing and replaying network traffic at full wire speed, but traffic can be limited to a specified value of bitrate at the output. The thesis is concluded by a comparison of the implemented application and the packet generator implemented on the NetFPGA platform. According to this comparison, the implemented application is better than the NetFPGA packet generator.
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IPv6 Prefix Sets Generator
Utkin, Kirill ; Kučera, Jan (referee) ; Matoušek, Jiří (advisor)
Due to the fast adoption of IPv6 protocol, number of IPv6 prefixes in routing tables are incessantly increasing. Based on this fact, development of new lookup algorithms is required. However, testing of those algorithms is highly dependent on size of datasets, which are not large enough for this purpose at the moment. Design and implementation of generator of IPv6 prefix sets, which will be based on currently using address allocation policies, is the main goal of this bachelor's thesis. Implementation of generator was preceded by study and implementation of the generator V6Gene. Validation of generated datasets were performed by comparing length distribution and level distribution of prefixes with the real world datasets. Finally, speed of the generating process and memory usage were compared for implemented generators.
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Analysis of Parameters of Packet Classification Rule Sets
Sabo, Jozef ; Orsák, Michal (referee) ; Matoušek, Jiří (advisor)
A theme of bachelor's thesis is an analysis of rules used for packet classification in computer networks. A theoretical part of the thesis introduces packet classification and describes the role of classification rules. This part also presents the format of classification rules utilized in real tools. Based on these information, a tool able to analyze IP 5-tuple classification rules in any format was designed and implemented. Output of the implemented tool is a parameter file containing different statistics and probability distributions of examined rule sets. This parameter file can be used for generating synthetic rule sets using ClassBench and ClassBench-ng tools. The final part of the thesis examines parameter files created by the implemented tool from available real rule sets.
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IPv6 Prefix Generator
Obrusník, Vojtěch ; Kučera, Jan (referee) ; Matoušek, Jiří (advisor)
Incoming deployment of IPv6 technology in larger scale requires existence of effective route lookup algorithms suitable of manipulation with long IPv6 prefixes. Development of such algorithms is dependent on an huge amount of test data sets, which do not exist at the moment. This paper is focused on design and implementation of a tool, that would be able to generate such test data sets. Study phase of IPv6 address allocation polices and analysis of currently available pieces of prefix sets took place before the implementation. Validation of results was performed by bit value and prefix length scatter measurement.
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Comparison of IPv6 Prefix Set Generators
Vašek, Dominik ; Kučera, Jan (referee) ; Matoušek, Jiří (advisor)
This bachelor's thesis aims to compare the IPv6 generators. In the first part we introduce protocol IPv6 and the allocation policies of registrars in order to better understand the problem. Next, we introduce three existing prefix set generators, whose description is available. In the second part of the thesis we propose and implement a series of tests for the prefix set generators. Lastly, we test the generators and make a conclusion based on the results. According to our results, we conclude that the prefix sets from the NonRandom and IPv6Table generators have a large error in comparison with a target prefix set. However, V6Gene, the implementation of which is not currently publicly available, might generate prefix sets close to the reality based on its proposal.
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High-Speed Packet DMA Transfers from FPGA
Kubálek, Jan ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
Computer network devices that implement data-flow monitoring to allow network manage-ment require a high-speed receiving of a large amount of data for analysis. For a deviceto enable the monitoring of a network with high data traffic, its network interface cardneeds to be capable of transferring received data to a RAM at high speed. A new mo-dule for an FPGA chip on a network interface card, which can control these transfers, wasdesigned, implemented and tested in the course of this thesis. The created module sup-ports transfer of packets from the FPGA to the computer's memory via a PCI-Express busat the speed of 100 Gb/s and 200 Gb/s. Packets are transferred by DMA in system DPDK.
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Automatic Configuration of Utility Tools for FPGA Firmware
Perešíni, Martin ; Matoušek, Jiří (referee) ; Kučera, Jan (advisor)
This bachelor's thesis is about designing an automatic configuration of utility tools for FPGA firmware. The assignment is solved within CESNET research activity, which is devoted on the development of hardware-accelerated network interface cards based on FPGA technology. The aim of the thesis is to replace current inflexible system for describing the firmware structure used by NIC, HANIC and SDM projects. The system was based on a firmware description by XML file, which was created manually for each configuration. Based on negative aspects of system is created new design, which is using Device Tree. Device Tree is opening possibility to change NetCOPE build system for automatic generating firmware description. Description of hardware is distributed together with firmware. In the thesis, the design of the system was implemented and then verified by testing functionality on the ethctl tool. At the end of the work are mentioned possible system features and extensions for future.
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Generation of Binary Prefix Tree According to Probabilistic Parameters
Ženčák, Tomáš ; Kučera, Jan (referee) ; Matoušek, Jiří (advisor)
The goal of this work is to create a prefix set generator which will be capable of generating a prefix set from parameters specified in the ClassBench toolset. This work describes a possible approach to generation, as well as the final algorithm for prefix set generation. The resulting generator is able to generate prefix sets whose average deviation from the target parameters is typically orders of magnitude lower than the deviation of sets generated by ClassBench.
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Acceleration of LZ4 Compression Algorithm in FPGA
Marton, Dominik ; Martínek, Tomáš (referee) ; Matoušek, Jiří (advisor)
This project describes the implementation of an LZ4 compression algorithm in a C/C++-like language, that can be used to generate VHDL programs for FPGA integrated circuits embedded in accelerated network interface controllers (NICs). Based on the algorithm specification, software versions of LZ4 compressor and decompressor are implemented, which are then transformed into a synthesizable language, that is then used to generate fully functional VHDL code for both components. Execution time and compression ratio of all implementations are then compared. The project also serves as a demonstration of usability and influence of high-level synthesis and high-level approach to design and implementation of hardware applications known from common programming languages.
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