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Software for digital filter verification
Tesařík, Jan ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
Diploma thesis deals with design of verification environment for analyzing systems with digital filters. Verification environment is written in SystemVerilog language and it is generated by program, which is also providing generation of input data for system of filters. Matlab environment is used for gaining the reference data. The simulation of the designed involvement with digital filters is performed by program ModelSim. The most watched parameter is functional coverage which indicates how big part of the HDL description has been tested.
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Design of bandpass digital filter
Dvořák, Vojtěch ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
The aim of this work is to explain the problems of digital IIR filters, demostrate process of designing digital filters in Matlab and design a model of ideal band-pass filter with concrete parameters in Matlab. This filter will then serve as a reference model for verification with the filter described in VHDL.
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Industrial HD camera interface
Juřica, Libor ; Dvořák, Vojtěch (referee) ; Bohrn, Marek (advisor)
Master´s thesis deals with creating circuit for receiving data from industrial camera. IP Core is designing for FPGA. Theoretical part of the work describes SDI interface, analysis of relevant SMPTE standards and specification of data format. The thesis include general characteristics of multigigabit transceivers. Practical part include VHDL description of SDI receiver. Thesis presents simulations of created circuit, implementation for real application and measurement results for signal transmission over slip ring.
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Implementation of fast serial bus on FPGA
Drbal, Jakub ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources.
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FFT implementation in FPGA and ASIC
Dvořák, Vojtěch ; Bohrn, Marek (referee) ; Fujcik, Lukáš (advisor)
The aim of this thesis is to design the implementation of fast Fourier transform algorithm, which can be used in FPGA or ASIC circuits. Implementation will be done in Matlab and then this form of implementation will be used as a reference model for implementation of fast Fourier transform algorithm in VHDL. To verify the correctness ofdesign verification enviroment will be created and verification process wil be done. Program that will generate source code for various parameters of the module performing a fast Fourier transform will be created in the last part of this thesis.
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Fenologie lesních dřevin ve smíšeném porostu na polesí Bílovice nad Svitavou
Dvořák, Vojtěch
The phenological research was inquired into the Sessile Oak (Querus petraea Matt. Liebl.) and European Larch (Larix decidua Mill.) on the explorative area of ŠLP ML Křtiny which belongs to the forest district of Bílovice nad Svitavou. These two trees were in the 35 years old mixed stand. On the monitored trees, there were compared the beginnings and the durations of the particular phenological stages in the connection with the weather conditions in the particular year. The temperature fluctuations for the phenological stages were specified by sum of effective air temperatures higher than 5 °C and 0 °C. There were compared the duration of the spring and autumn phenological stages on the Sessile Oak and European Larch. The gained results were compared with the statements of other authors in the Czech Republic and abroad. There were also done the comparison of the beginnings and durations of particular phenological stages of the trees with the datas of the long--standing observation ČHMÚ on the area of the same height above sea level in the Czech Republic.
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