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Visualization of forward error correction securing by block and cyclical codes
Fančal, Petr ; Číž, Radim (referee) ; Šilhavý, Pavel (advisor)
This bachelor thesis provides an introduction to the principles of forward error correction securing by linear block and cyclical systematic codes and its visualization by educational application. First part of the thesis contains comprehensive theoretical base of principles of forward error correction securing and capability of linear block and cyclical systematic codes. Second part describes the educational application, realized in graphical user interface GUI of MATLAB. This application step by step visualizes parts of procedures of securing, error detection and correction. Its main benefit is its usability as illustrative teaching aid.
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Design and Implementation of a Codec for Iwadari Code
Křivánek, Jan ; Drábek, Vladimír (referee) ; Sekanina, Lukáš (advisor)
This thesis deals with the design, the implementation and oncoming testing of circuits implementing the encoder and the decoder of the Iwadari code with universal correction ability. The design according to the theory of forward error correction systems is well-founded by mathematic modeling. Describing of the implementation prefers VHDL language. The implemented encoder and decoder were simulated in specialized development environments to verify their correct operation. Final demonstrational physical implementation of testing connection of the encoder and the decoder in experimental educational platform FIT-kit was made to show their function and mechanism.
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Turbo codes and their applications in transmission technologies
Kuvik, Michal ; Číž, Radim (referee) ; Šilhavý, Pavel (advisor)
Purpose of this work is to clarify problems of anti-error security with the help of turbo codes. This work can be divided into two parts. In the first part we look at the theoretical aspect of features of turbo codes, their coding and at various approaches of decoding secure messages for example SOVA and MAP, also at analyzing usage of turbo codes in promising transmission technologies. Second part is focused on creating an application with the help of software Matlab and on verifying attributes of this method in this software.
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RS-FEC layer implementation for 400Gb/s ethernet
Zahálka, Patrik ; Kekely, Lukáš (referee) ; Vyroubal, Petr (advisor)
Tato diplomová práce se věnuje problematice VLSI návrhu a implementaci vrstvy RS-FEC pro 400 Gb/s Ethernet do FPGA Intel® Stratix® 10 DX 2100. V práci je charakterizován současný stav rychlostí Ethernetu, význam a kontext samoopravných kódů v rámci protokolu Ethernet. Dále je popsána výroba PLD čipů i matematická podstata RS sa moopravných kódů. V části praktické je představen návrh řešení systému RS-FEC, který byl realizován genericky pomocí jazyka VHDL. Zároveň byly jeho komponenty implementovány a v závěrečné diskusi je popsáno jeho řešení, dosažené výsledky včetně jeho budoucího rozšíření.
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RS-FEC layer implementation for 400Gb/s ethernet
Zahálka, Patrik ; Kekely, Lukáš (referee) ; Vyroubal, Petr (advisor)
Tato diplomová práce se věnuje problematice VLSI návrhu a implementaci vrstvy RS-FEC pro 400 Gb/s Ethernet do FPGA Intel® Stratix® 10 DX 2100. V práci je charakterizován současný stav rychlostí Ethernetu, význam a kontext samoopravných kódů v rámci protokolu Ethernet. Dále je popsána výroba PLD čipů i matematická podstata RS sa moopravných kódů. V části praktické je představen návrh řešení systému RS-FEC, který byl realizován genericky pomocí jazyka VHDL. Zároveň byly jeho komponenty implementovány a v závěrečné diskusi je popsáno jeho řešení, dosažené výsledky včetně jeho budoucího rozšíření.
|
|
|
Design and Implementation of a Codec for Iwadari Code
Křivánek, Jan ; Drábek, Vladimír (referee) ; Sekanina, Lukáš (advisor)
This thesis deals with the design, the implementation and oncoming testing of circuits implementing the encoder and the decoder of the Iwadari code with universal correction ability. The design according to the theory of forward error correction systems is well-founded by mathematic modeling. Describing of the implementation prefers VHDL language. The implemented encoder and decoder were simulated in specialized development environments to verify their correct operation. Final demonstrational physical implementation of testing connection of the encoder and the decoder in experimental educational platform FIT-kit was made to show their function and mechanism.
|
|
|
Turbo codes and their applications in transmission technologies
Kuvik, Michal ; Číž, Radim (referee) ; Šilhavý, Pavel (advisor)
Purpose of this work is to clarify problems of anti-error security with the help of turbo codes. This work can be divided into two parts. In the first part we look at the theoretical aspect of features of turbo codes, their coding and at various approaches of decoding secure messages for example SOVA and MAP, also at analyzing usage of turbo codes in promising transmission technologies. Second part is focused on creating an application with the help of software Matlab and on verifying attributes of this method in this software.
|
|
|
Visualization of forward error correction securing by block and cyclical codes
Fančal, Petr ; Číž, Radim (referee) ; Šilhavý, Pavel (advisor)
This bachelor thesis provides an introduction to the principles of forward error correction securing by linear block and cyclical systematic codes and its visualization by educational application. First part of the thesis contains comprehensive theoretical base of principles of forward error correction securing and capability of linear block and cyclical systematic codes. Second part describes the educational application, realized in graphical user interface GUI of MATLAB. This application step by step visualizes parts of procedures of securing, error detection and correction. Its main benefit is its usability as illustrative teaching aid.
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