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Implementation of cryptographic algorithms on the FPGA platform
Zugárek, Adam ; Sládok, Ondřej (referee) ; Smékal, David (advisor)
This bachelor’s thesis describes methods of data encryption and author’s own implementation on FPGA. The goal of this thesis is to implement cipher on a hardware accelerated network card COMBO. In the introduction is described encryption using block ciphers. Cipher AES was chosen to implement, which is famous and most using cipher. Its detailed description is described in the first part of the thesis. In the second part is described the author’s own implementation of AES cipher in VHDL. In the next part is method of interconnecting the resulting program with a framework of the FPGA card – NetCOPE. Achieved results are in the end of this thesis. The resulting program cannot encrypt network communication. It only transforms data stored in the card, which then send to host computer.
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Hardware accelerated data transfer using TLS protocol
Zugárek, Adam ; Pokorný, Jiří (referee) ; Smékal, David (advisor)
This paper describes implementation of the whole cryptographic protocol TLS including control logic and used cryptographic systems. The goal is to implement an application in the FPGA technology, so it could be used in hardware accelerated network card. The reason for this is new supported higher transmission speeds that Ethernet is able to operate on, and the absence of implementation of this protocol on FPGA. In the first half of this paper is described theory of cryptography followed by description of TLS protocol, its development, structure and operating workflow. The second half describes the implementation on the chosen technology that is also described here. It is used already existing solutions of given cryptographic systems for the implementation, or at least their parts that are modified if needed for TLS. It was implemented just several parts of whole protocol, such are RSA, Diffie-Hellman, SHA and part of AES. Based on these implementations and continuing studying in this matter it was made conclusion, that FPGA technology is inappropriate for implementation of TLS protocol and its control logic. Recommendation was also made to use FPGA only for making calculations of given cryptographic systems that are controlled by control logic from software implemented on standard processors.
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Hardware accelerated data transfer using TLS protocol
Zugárek, Adam ; Pokorný, Jiří (referee) ; Smékal, David (advisor)
This paper describes implementation of the whole cryptographic protocol TLS including control logic and used cryptographic systems. The goal is to implement an application in the FPGA technology, so it could be used in hardware accelerated network card. The reason for this is new supported higher transmission speeds that Ethernet is able to operate on, and the absence of implementation of this protocol on FPGA. In the first half of this paper is described theory of cryptography followed by description of TLS protocol, its development, structure and operating workflow. The second half describes the implementation on the chosen technology that is also described here. It is used already existing solutions of given cryptographic systems for the implementation, or at least their parts that are modified if needed for TLS. It was implemented just several parts of whole protocol, such are RSA, Diffie-Hellman, SHA and part of AES. Based on these implementations and continuing studying in this matter it was made conclusion, that FPGA technology is inappropriate for implementation of TLS protocol and its control logic. Recommendation was also made to use FPGA only for making calculations of given cryptographic systems that are controlled by control logic from software implemented on standard processors.
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|
|
Implementation of cryptographic algorithms on the FPGA platform
Zugárek, Adam ; Sládok, Ondřej (referee) ; Smékal, David (advisor)
This bachelor’s thesis describes methods of data encryption and author’s own implementation on FPGA. The goal of this thesis is to implement cipher on a hardware accelerated network card COMBO. In the introduction is described encryption using block ciphers. Cipher AES was chosen to implement, which is famous and most using cipher. Its detailed description is described in the first part of the thesis. In the second part is described the author’s own implementation of AES cipher in VHDL. In the next part is method of interconnecting the resulting program with a framework of the FPGA card – NetCOPE. Achieved results are in the end of this thesis. The resulting program cannot encrypt network communication. It only transforms data stored in the card, which then send to host computer.
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