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Implementation of Self-Correcting Codes for 100 Gb/s Ethernet
Velecký, Jan ; Kučera, Jan (referee) ; Kekely, Lukáš (advisor)
The thesis deals with the design of entire RS-FEC layer for the 100 Gb/s Ethernet according to IEEE 802.3-2015 standard including Reed-Solomon encoder and decoder. Text clarifies mathematical basis of finite fields, linear block codes, cyclic codes and particularly Reed-Solomon codes used in design. Design of RS-FEC layer transmit side has been adjusted for implementation in COMBO network cards which use Xilinx Virtex-7 FPGA and realized in VHDL. Encoder has been optimized in several steps - as for FPGA resource usage and as for VHDL code synthesis duration. Reduction of resource usage has been achieved by using pipelining thanks to properties of cyclic codes. Synthesis duration then by creating logic of encoder on gate level on its own. Resulting implementation has been tested in simulation and it is optimized enough for usage in FPGA for Ethernet implementation. It is possible to adapt both design and implementation for 400Gb/s Ethernet which does not exist yet at the time of design.
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Prediction of the Effect of Mutation on Protein Solubility
Velecký, Jan ; Martínek, Tomáš (referee) ; Hon, Jiří (advisor)
The goal of the thesis is to create a predictor of the effect of a mutation on protein solubility given its initial 3D structure. Protein solubility prediction is a bioinformatics problem which is still considered unsolved. Especially a prediction using a 3D structure has not gained much attention yet. A relevant knowledge about proteins, protein solubility and existing predictors is included in the text. The principle of the designed predictor is inspired by the Surface Patches article and therefore it also aims to validate the results achieved by its authors. The designed tool uses changes of positive regions of the electric potential above the protein's surface to make a prediction. The tool has been successfully implemented and series of computationally expensive experiments have been performed. It was shown that the electric potential, hence the predictor itself too, can be successfully used just for a limited set of proteins. On top of that, the method used in the article correlates with a much simpler variable - the protein's net charge.
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Prediction of the Effect of Mutation on Protein Solubility
Velecký, Jan ; Martínek, Tomáš (referee) ; Hon, Jiří (advisor)
The goal of the thesis is to create a predictor of the effect of a mutation on protein solubility given its initial 3D structure. Protein solubility prediction is a bioinformatics problem which is still considered unsolved. Especially a prediction using a 3D structure has not gained much attention yet. A relevant knowledge about proteins, protein solubility and existing predictors is included in the text. The principle of the designed predictor is inspired by the Surface Patches article and therefore it also aims to validate the results achieved by its authors. The designed tool uses changes of positive regions of the electric potential above the protein's surface to make a prediction. The tool has been successfully implemented and series of computationally expensive experiments have been performed. It was shown that the electric potential, hence the predictor itself too, can be successfully used just for a limited set of proteins. On top of that, the method used in the article correlates with a much simpler variable - the protein's net charge.
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Implementation of Self-Correcting Codes for 100 Gb/s Ethernet
Velecký, Jan ; Kučera, Jan (referee) ; Kekely, Lukáš (advisor)
The thesis deals with the design of entire RS-FEC layer for the 100 Gb/s Ethernet according to IEEE 802.3-2015 standard including Reed-Solomon encoder and decoder. Text clarifies mathematical basis of finite fields, linear block codes, cyclic codes and particularly Reed-Solomon codes used in design. Design of RS-FEC layer transmit side has been adjusted for implementation in COMBO network cards which use Xilinx Virtex-7 FPGA and realized in VHDL. Encoder has been optimized in several steps - as for FPGA resource usage and as for VHDL code synthesis duration. Reduction of resource usage has been achieved by using pipelining thanks to properties of cyclic codes. Synthesis duration then by creating logic of encoder on gate level on its own. Resulting implementation has been tested in simulation and it is optimized enough for usage in FPGA for Ethernet implementation. It is possible to adapt both design and implementation for 400Gb/s Ethernet which does not exist yet at the time of design.
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