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National Repository of Grey Literature 1 records found  Search took 0.01 seconds. 
Implementation of system for IC testing via JTAG interface
 Prášil, Pavel ; Zachariášová, Marcela (referee) ; Petyovský, Petr (advisor)
This master thesis deals with testing integrated circuits containing RISC-V processor core using JTAG protocol. This thesis objective is to design a module for 2-wire JTAG protocol support and design of an extending protocol for RISC-V processor system bus access. Designed module will be used for the integrated circuit testing using a 2-wire JTAG interface in order to reduce the number of pins dedicated for JTAG interface. The extending protocol will be used to reduce time spent by integrated circuits testing. The thesis contains description of the RISC-V testing system, design and implementation of module for 2-wire JTAG protocol support and also design and implementation of module for system bus access by the extending protocol. The thesis also includes extension of testing SW environment by support of communication using the extending protocol and verification of HW solution functionality. The thesis contain evaluation of time efficiency of implemented communication solution.
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