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Methodology of highly reliable systems design
Straka, Martin ; Gramatová, Elena (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Methodology for fault tolerant system state synchronization design and its recovery from faults
Szurman, Karel ; Fišer, Petr (referee) ; Racek, Stanislav (referee) ; Vlček, Karel (referee) ; Kotásek, Zdeněk (advisor)
In this Ph.D. thesis, a new methodology for the fault tolerant system state synchronization design and its recovery from faults is presented. A state synchronization method designed by means of the proposed methodology allows to repair the state of sequential logic elements implemented in the FPGA application logic, which cannot be repaired by the partial dynamic reconfiguration. The proposed methodology describes possible state synchronization design methods with respect to TMR granularity, dependence of the system function on its previous states and the system architecture. The methodology focuses on coarse-grained TMR architectures and state synchronization in the systems controlled by means of finite state machines or a processor. The use of the methodology is demonstrated on the CAN bus control system and the microcontroller NEO430, for which specific synchronization methods were designed. The systems reliability and new ability of the systems for recovery from faults were verified in the presence of simulated SEU faults. The experimental results and the contribution of this thesis are discussed in the conclusion.
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Web Portal for VHDL Core Generator
Poupě, Petr ; Kaštil, Jan (referee) ; Straka, Martin (advisor)
In this Bachelor thesis, activities which aim at developing web portal for an intuitive access to VHDL core generators are presented. The basic principles of methodology for generating VHDL descriptions of hardware checkers for communication protocols and RTL circuits are demonstrated together with their impact on the fault tolerant architectures. The main goal of this work is to develop user-friendly web environment which would facilitate the use of VHDL core generators. The specification and features of web portal are described together with implementation details and testing of final application. As the results of this thesis, the web portal based on PHP and MySQL database was created.
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Web Portal for Fault Tolerant Methodology Application
Poupě, Petr ; Kaštil, Jan (referee) ; Mičulka, Lukáš (advisor)
This master's thesis deals with the development of web portal for the application of fault-tolerant methodologies. It introduces the issue of fault-tolerant systems and analyze system requirements, that have users working in this field. It describes the development cycle from analysis and specification of application system design through to implementation and testing part. More thoroughly it is focusing above design portal that provides a comprehensive and versatile solution to the problem that leads to the final implementation of this portal. This realization is part of the thesis.
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Secured control system
Kubáň, Michal ; Havlíček, Tomáš (referee) ; Pavlík, Michal (advisor)
This work deals with the design of a small hydro secured control system. The secured control system itself belongs to the Fault Tolerant Systems category. At first the requirements on small hydro control system are discussed. Then the introduction into the basics of Fault Tolerant System theory is given. The requirements on small hydro control system and basics of Fault Tolerant Systems are basis for specification of secured control system which design and construction is the main objective of this work.
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Methodology for fault tolerant system state synchronization design and its recovery from faults
Szurman, Karel ; Fišer, Petr (referee) ; Racek, Stanislav (referee) ; Vlček, Karel (referee) ; Kotásek, Zdeněk (advisor)
In this Ph.D. thesis, a new methodology for the fault tolerant system state synchronization design and its recovery from faults is presented. A state synchronization method designed by means of the proposed methodology allows to repair the state of sequential logic elements implemented in the FPGA application logic, which cannot be repaired by the partial dynamic reconfiguration. The proposed methodology describes possible state synchronization design methods with respect to TMR granularity, dependence of the system function on its previous states and the system architecture. The methodology focuses on coarse-grained TMR architectures and state synchronization in the systems controlled by means of finite state machines or a processor. The use of the methodology is demonstrated on the CAN bus control system and the microcontroller NEO430, for which specific synchronization methods were designed. The systems reliability and new ability of the systems for recovery from faults were verified in the presence of simulated SEU faults. The experimental results and the contribution of this thesis are discussed in the conclusion.
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Methodology of highly reliable systems design
Straka, Martin ; Gramatová, Elena (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Methodology of highly reliable systems design
Straka, Martin ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Web Portal for VHDL Core Generator
Poupě, Petr ; Kaštil, Jan (referee) ; Straka, Martin (advisor)
In this Bachelor thesis, activities which aim at developing web portal for an intuitive access to VHDL core generators are presented. The basic principles of methodology for generating VHDL descriptions of hardware checkers for communication protocols and RTL circuits are demonstrated together with their impact on the fault tolerant architectures. The main goal of this work is to develop user-friendly web environment which would facilitate the use of VHDL core generators. The specification and features of web portal are described together with implementation details and testing of final application. As the results of this thesis, the web portal based on PHP and MySQL database was created.
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Web Portal for Fault Tolerant Methodology Application
Poupě, Petr ; Kaštil, Jan (referee) ; Mičulka, Lukáš (advisor)
This master's thesis deals with the development of web portal for the application of fault-tolerant methodologies. It introduces the issue of fault-tolerant systems and analyze system requirements, that have users working in this field. It describes the development cycle from analysis and specification of application system design through to implementation and testing part. More thoroughly it is focusing above design portal that provides a comprehensive and versatile solution to the problem that leads to the final implementation of this portal. This realization is part of the thesis.
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