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National Repository of Grey Literature 2 records found  Search took 0.01 seconds. 
Data transmition security with Reed-Müller codes
 Hrouza, Ondřej ; Burda, Karel (referee) ; Němec, Karel (advisor)
The aim of this work is to propose a Reed-Muller code that secure data transfer to t = 4 independent errors, the information rate R ? 0,5 and for this code to produce a detailed proposal for implementation of the codec. In order to implement this proposal, it is necessary to familiarize themselves with the basic properties Reed-Muller codes. To understand the function of codec Reed-Muller code is in this thesis analyzed the process of encoding and decoding, which is based on a method of using the majority logic. For the design of codec, which consists of encoder and decoder, are used programmable logic circuits FPGA. These circuits are programmed in VHDL language, when for the design source codes is used Xilinx ISE 10.1. In thesis is examined in detail the structure and function of the encoder and decoder chosen Reed-Muller code and there are presented parts of the proposed source codes. Verify the functional ability of the codec is achieved by simulation in program ModelSim SE 5.7f. The simulation results together with the another proposal realization are output of this work.
Detailed record
Data transmition security with Reed-Müller codes
 Hrouza, Ondřej ; Burda, Karel (referee) ; Němec, Karel (advisor)
The aim of this work is to propose a Reed-Muller code that secure data transfer to t = 4 independent errors, the information rate R ? 0,5 and for this code to produce a detailed proposal for implementation of the codec. In order to implement this proposal, it is necessary to familiarize themselves with the basic properties Reed-Muller codes. To understand the function of codec Reed-Muller code is in this thesis analyzed the process of encoding and decoding, which is based on a method of using the majority logic. For the design of codec, which consists of encoder and decoder, are used programmable logic circuits FPGA. These circuits are programmed in VHDL language, when for the design source codes is used Xilinx ISE 10.1. In thesis is examined in detail the structure and function of the encoder and decoder chosen Reed-Muller code and there are presented parts of the proposed source codes. Verify the functional ability of the codec is achieved by simulation in program ModelSim SE 5.7f. The simulation results together with the another proposal realization are output of this work.
Detailed record

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