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Modelling of Neural Network Hardware Accelerators
 Klhůfek, Jan ; Sekanina, Lukáš (referee) ; Mrázek, Vojtěch (advisor)
The aim of this master thesis is modeling of neural network accelerators with HW support for quantization. The thesis first focuses on the concept of computation in convolutional neural networks (CNNs) and introduces different categories of hardware architectures that are used for their processing. Following this, optimization techniques for CNN models are summarized, with the goal of achieving efficient processing on specialized hardware architectures. The subsequent part of the thesis involves a comparison of existing analytical tools that are used to estimate hardware performance parameters during inference and which can be expanded to incorporate quantization support. Based on an experimental comparison, the Timeloop tool was selected for the purposes of this thesis. A thorough explanation of this tool's functionality is presented, along with a concept and implementation of its expansion to support quantization. In conclusion, the thesis experimentally tests the impact of various quantization configurations on evaluated inference parameters across different hardware architectures.
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