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A Test Interface for Integrated Circuits with the Small Number of Pins
Tománek, Jakub ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This study explores the possibilities for reducing the number of pins needed for scan mode interface. In the first part of this paper the existing solutions and methods that are usable for this purpose are described. Specific four pin, three pin, two pin, one pin and zero pin interfaces are designed in second part. Advantages and disadvantages of existing solutions and methods as well as designed and proposed interface are summarized in the conclusion.
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Test Application Methodology Based On the Identification of Testable blocks
Herrman, Tomáš ; Plíva, Zdeněk (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
The PhD thesis deals with the analysis of digital systems described on RT level. The methodology of data paths analysis is decribed, the data path controller analysis is not solved in the thesis. The methodology is built on the concept of Testable Block (TB) which allows to divide digital component to such segments which can be tested through their inputs/outputs, border registers and primary inputs/outputs are used for this purpose. As a result, lower number of registers is needed to be included into scan chain - border registers are the only ones which are scanned. The segmentation allows also to reduce the volume of test vectors, tests are generated for segments, not for the complete component. To identify TBs, two evolutionary algorithms are used, they operate on TB formal model which is also defined in the thesis.
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A Test Interface for Integrated Circuits with the Small Number of Pins
Tománek, Jakub ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This study explores the possibilities for reducing the number of pins needed for scan mode interface. In the first part of this paper the existing solutions and methods that are usable for this purpose are described. Specific four pin, three pin, two pin, one pin and zero pin interfaces are designed in second part. Advantages and disadvantages of existing solutions and methods as well as designed and proposed interface are summarized in the conclusion.
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|
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Test Application Methodology Based On the Identification of Testable blocks
Herrman, Tomáš ; Plíva, Zdeněk (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
The PhD thesis deals with the analysis of digital systems described on RT level. The methodology of data paths analysis is decribed, the data path controller analysis is not solved in the thesis. The methodology is built on the concept of Testable Block (TB) which allows to divide digital component to such segments which can be tested through their inputs/outputs, border registers and primary inputs/outputs are used for this purpose. As a result, lower number of registers is needed to be included into scan chain - border registers are the only ones which are scanned. The segmentation allows also to reduce the volume of test vectors, tests are generated for segments, not for the complete component. To identify TBs, two evolutionary algorithms are used, they operate on TB formal model which is also defined in the thesis.
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