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A Digital Network-on-chip Architecture Model for Diagnostics
Valachovič, Marek ; Bohrn, Marek (referee) ; Šťáva, Martin (advisor)
Due to increasing integration on the chip, bus structure for on-chip comunication is less and less advantageous. For this reason, Network on Chip (NoC) was created as a solution to this problém. In this work, the basic blocks of the NoC architecture are described. The model of this architecture called Nonfire is described in detail, both function blocks, from which the router is created, and the network Interface Connecting this router with the Processing Element.
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On The Efficiency Of Precise Fault Localization And Identification In No
Valachovič, Marek
The paper joins the Bonfire NoC model, desrcibed in VHDL, together with a method of the precise localization and identification of faults in NoC and sums up a few findings about the efficiency of fault-tolerant NoC employing the method. A special focus is given to the area overhead and the mean time between failures in the presence of no or one permanent fault and some transient faults.
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A Digital Network-on-chip Architecture Model for Diagnostics
Valachovič, Marek ; Bohrn, Marek (referee) ; Šťáva, Martin (advisor)
Due to increasing integration on the chip, bus structure for on-chip comunication is less and less advantageous. For this reason, Network on Chip (NoC) was created as a solution to this problém. In this work, the basic blocks of the NoC architecture are described. The model of this architecture called Nonfire is described in detail, both function blocks, from which the router is created, and the network Interface Connecting this router with the Processing Element.
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