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National Repository of Grey Literature 1 records found  Search took 0.01 seconds. 
Implementation of video compression into FPGA chip
 Tomko, Jakub ; Fujcik, Lukáš (referee) ; Bohrn, Marek (advisor)
This thesis is focused on the compression algorithm's analysis of MJPEG format and its implementation in FPGA chip. Three additional video bitstream reduction methods have been evaluated for real-time low latency applications of MJPEG format. These methods are noise filtering, inter-frame encoding and lowering video's quality. Based on this analysis, a MJPEG codec has been designed for implementation into FPGA chip XC6SLX45, from Spartan-6 family.
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